ASIC Digital Design Engineer, Architect-18709
Originally posted 13 September 2026 by the employer.
Define and execute new architecture for protocols like Universal Accelerator Link (UAL).
About the role
This role involves defining and developing ASIC RTL design and verification at both chip and block levels.
What you'll do
- Define and develop ASIC RTL design and verification at both chip and block levels.
- Create and execute design plans for complex digital designs, focusing on DDR, PCIe, CXL, UAL, UCIe IO protocols.
- Collaborate with cross-functional teams to ensure seamless integration and functionality of designs.
- Utilize advanced design and verification methodologies and tools to achieve high-quality results.
- Mentor and guide junior engineers, promoting best practices and continuous improvement.
- Communicate with internal and external stakeholders to align on project goals and deliverables.
What you'll need
- BSEE or BSCE with 12+ years or an advanced degree with 10+ years industry experience.
- Extensive experience in ASIC RTL design.
- In-depth knowledge of DDR, PCIe, UAL, UCIe and similar IO protocols and their applications.
- Proficiency in advanced digital design tools and methodologies.
- Strong problem-solving skills and ability to work independently.
- Excellent communication skills for effective collaboration with diverse teams.
This role has been open 30 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1021
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1021 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 84 | 1021 |
| Open roles in the wider Digital Design & Verification family | 167 | 3191 · 115 employers |
| Median days open | 29 d | 61 d (−32 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 134 open roles · median 64 d
- Synopsys (this employer) · 86 open roles · median 29 d
- AMD · 72 open roles · median 35 d
- Analog Devices · 49 open roles · median 47 d
- NVIDIA · 46 open roles · median 63 d
- NXP Semiconductors · 41 open roles · median 84 d
How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.