ASIC Design Verification Lead - Saratoga, CA, United States
About the role
This senior technical leadership role focuses on driving verification strategy, infrastructure, and closure for complex, high-performance networking silicon.
What you'll do
- Define and own block-, subsystem-, and chip-level verification strategies.
- Develop and maintain scalable verification environments using SystemVerilog and UVM.
- Drive execution from test-plan definition through coverage and bug closure.
- Write and review testbenches, sequences, checkers, and scoreboards.
- Debug functional failures across RTL, testbench, and simulation environments.
- Partner with RTL, architecture, physical design, and firmware teams.
What you'll need
- Strong hands-on experience in ASIC design verification.
- Proven track record of taking at least one complex ASIC to tape-out with direct verification ownership.
- Deep expertise in SystemVerilog and UVM-based verification methodologies.
- Strong understanding of ASIC design and verification flows, including simulation, coverage, and debug.
- Experience with block-level through full-chip verification and integration.
- Ability to drive execution in ambiguous environments.
Nice to have
- Networking ASIC verification experience (Ethernet-based systems preferred).
- Experience with gate-level, timing-aware, and low-power verification.
- Familiarity with high-speed interfaces and chip-to-chip interconnects.
- Experience with emulation, acceleration, or FPGA-based validation.
- Post-silicon debug experience and RTL-to-silicon correlation.
Skills: UVM, SystemVerilog, testbenches, functional coverage, bug closure
This role has been open 1 day — well below the 62-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1160
|
Median days open
62 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Eridu AI | All employers we track in this specialty (1160 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1160 |
| Open roles in the wider Digital Design & Verification family | 6 | 3050 · 114 employers |
| Median days open | 90 d | 62 d (+28 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: UVM, SystemVerilog, testbenches, functional coverage, bug closure
Who's hiring in this category
- AMD · 101 open roles · median 37 d
- Qualcomm · 97 open roles · median 51 d
- NVIDIA · 85 open roles · median 69 d
- Synopsys · 65 open roles · median 22 d
- SiFive · 56 open roles · median 54 d
- NXP Semiconductors · 51 open roles · median 80 d
How we counted: 1160 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 27 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.