ASIC Design Verification Engineer (Santa Clara, CA)
$107,400 - $161,200 USD yearly
Originally posted 19 August 2026 by the employer.
About the role
This role is for an ASIC Design Verification Engineer responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support, with a focus on digital power IP's.
What you'll do
- Develop comprehensive pre-silicon test plans for digital power IP's.
- Develop testbenches using SystemVerilog-UVM.
- Develop coverage and assertion models.
- Deploy power-aware UPF verification flow and methodology.
- Develop automation to improve verification efficiency.
- Perform formal verification (property checking).
What you'll need
- 3+ years of DV experience using UVM/assertion based verification technologies.
- Experience in verifying complex SOC or SOC subsystems.
- Experience with caches and DDR memory protocol verification.
- Experience with using memory verification VIP's.
- Exposure to DDR phy.
- Exposure to firmware/driver development using C.
- Exposure with multiple successful tapeouts from conception to post silicon debug.
- Exposure to Formal verification.
- Exposure to PASIM simulations.
- Exposure to perf and power verification.
- Skill proficiency in UVM, SystemVerilog, assertion, C, and Python.
Skills: UVM, System Verilog, assertion, DDR memory protocol, SOC subsystems
This role has been open 57 days — below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1195
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1195 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 110 | 1195 |
| Open roles in the wider Digital Design & Verification family | 383 | 3198 · 115 employers |
| Median days open | 37 d | 64 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: UVM, System Verilog, assertion, DDR memory protocol, SOC subsystems
Who's hiring in this category
- Qualcomm (this employer) · 109 open roles · median 37 d
- AMD · 97 open roles · median 51 d
- NVIDIA · 84 open roles · median 58 d
- Synopsys · 63 open roles · median 31 d
- SiFive · 55 open roles · median 73 d
- Arm Holdings · 49 open roles · median 101 d
How we counted: 1195 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.