ASIC Design Verification Engineer, Amazon Leo - San Diego, California, United States
Originally posted 7 October 2026 by the employer.
Join the Amazon Leo sub-team defining and implementing digital chip SOCs for low Earth orbit satellites.
About the role
This role involves defining and implementing digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways within Amazon Leo's sub-team.
What you'll do
- Develop detailed test plans and write tests, run regressions, collect coverage matrices, and report progress.
- Write tests in C/C++ to execute on embedded CPU.
- Develop tests for FPGA and emulation platforms.
- Run formal verification of complex blocks to ensure functional correctness.
- Work with the design and communication systems team and participate in system-level verification using UVM, System C, and DPI-C test benches.
- Develop a highly automated environment to run regressions for builds and database organization.
What you'll need
- Proficiency in developing detailed test plans and writing tests.
- Experience with C/C++ for embedded CPU testing.
- Knowledge of FPGA and emulation platforms.
- Expertise in formal verification of complex blocks.
- Experience with UVM, System C, and DPI-C test benches for system-level verification.
- Ability to develop automated regression environments.
This role has been open 1 day — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1206
|
Median days open
63 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (1206 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 1206 |
| Open roles in the wider Digital Design & Verification family | 26 | 3180 · 113 employers |
| Median days open | 41 d | 63 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Who's hiring in this category
- Qualcomm · 111 open roles · median 42 d
- AMD · 102 open roles · median 49 d
- NVIDIA · 76 open roles · median 62 d
- Synopsys · 61 open roles · median 25 d
- SiFive · 55 open roles · median 66 d
- Micron Technology · 52 open roles · median 98 d
How we counted: 1206 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.