ASIC Design-for-Test (DFT) Engineer Intern - US-CO-Col Springs-Bldg C, United States
Originally posted 15 September 2026 by the employer.
This role focuses on Design-for-Test (DFT) methodologies for advanced integrated circuits.
About the role
This role provides hands-on experience across the semiconductor product development lifecycle, with a focus on Design-for-Test (DFT) methodologies used to ensure the manufacturability, quality, and reliability of advanced integrated circuits. You will work on real ASIC programs, gaining exposure to industry-standard EDA tools and flows.
What you'll do
- Support the development and verification of DFT architectures for complex digital and mixed-signal ASICs
- Apply industry-standard DFT methodologies, including scan insertion, scan compression, ATPG, Streaming Scan Networks, and memory BIST (MBIST)
- Assist with ATPG pattern generation, coverage analysis, and debug using Siemens Tessent
- Develop scripts and automation solutions using Python, Ruby, Tcl, or similar languages
- Collaborate with ASIC design, verification, physical design, and product engineering teams to ensure testability requirements are incorporated
- Participate in silicon bring-up, characterization, debug, and failure analysis activities
What you'll need
- Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
- Completion of sophomore year or higher by Summer 2027
- Coursework in Digital Logic Design, Computer Architecture, VLSI Design, or FPGA Design
- Understanding of digital circuits, finite state machines, and computer hardware fundamentals
- Programming or scripting experience in Python, C/C++, Tcl, or Ruby
Nice to have
- Familiarity with Verilog, SystemVerilog, or VHDL
- Knowledge of Linux/Unix environments and scripting
- Exposure to ASIC design flows, RTL development, simulation, or verification
- Familiarity with DFT concepts such as scan chains, ATPG, boundary scan, test compression, or memory BIST
- Exposure to EDA tools such as Siemens Tessent, Synopsys TestMAX, or Cadence Modus
- Demonstrated ability to work independently while managing multiple technical tasks and priorities
This role has been open 31 days — well below the 57-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
242
|
Median days open
57 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Keysight Technologies | All employers we track in this specialty (242 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 242 |
| Open roles in the wider Digital Design & Verification family | 7 | 3205 · 115 employers |
| Median days open | 31 d | 57 d (−26 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Who's hiring in this category
- AMD · 39 open roles · median 43 d
- NVIDIA · 23 open roles · median 35 d
- Qualcomm · 23 open roles · median 100 d
- NXP Semiconductors · 18 open roles · median 65 d
- Synopsys · 14 open roles · median 24 d
- Micron Technology · 10 open roles · median 64 d
How we counted: 242 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.