ASIC Design Engineer, Tools and Methodology Development - TX, Austin, United States
$116,000 - $218,500 USD yearly
Originally posted 8 September 2026 by the employer.
About the role
This role involves developing and deploying in-house tools and workflows to support engineering business units across NVIDIA.
What you'll do
- Develop and deploy in-house tools and workflows to support engineering business units.
- Take ownership of tools that verify common design blocks used in products.
- Act as a "DevOps" engineer for automated RTL generation.
- Build new workflows and methodologies for smooth integration into IP development environments.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering (or equivalent experience).
- 3+ years of experience.
- Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.
- Proficiency in scripting using Python and/or Perl.
- Experience with Unix/Linux shell scripting and Makefiles.
- Strong ability to collaborate with multi-functional teams and effectively communicate technical details.
Nice to have
- Prior experience in ASIC verification.
- Knowledge of Clocks/Resets design and verification.
- Exposure to CDC related design/verification flows.
- Exposure to backend flows (Synthesis, Timing, etc).
Skills: in-house tools, workflows, RTL generation, Verilog, Python
This role has been open 36 days — well below the 78-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
688
|
Median days open
78 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (688 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 37 | 688 |
| Open roles in the wider Physical Implementation family | 86 | 1469 · 108 employers |
| Median days open | 79 d | 78 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: in-house tools, workflows, RTL generation, Verilog, Python
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 168 d
- Synopsys · 65 open roles · median 38 d
- Micron Technology · 44 open roles · median 80 d
- Qualcomm · 41 open roles · median 66 d
- NVIDIA (this employer) · 39 open roles · median 79 d
- GlobalFoundries · 33 open roles · median 35 d
How we counted: 688 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.