ASIC Design Engineer, Principal - Austin, TX, United States
$225,000 - $350,000 USD yearly
About the role
This Principal ASIC Design Engineer role involves defining, implementing, and delivering critical IP blocks and subsystems for Positron AI’s inference ASICs/SoCs. The role focuses on owning the microarchitecture from high-level concept through RTL signoff, with an emphasis on HBM/DDR, PCIe/CXL, and AXI/ACE/CHI interfaces.
What you'll do
- Define and document microarchitecture for complex IP blocks/subsystems.
- Deliver production-quality, parameterized SystemVerilog RTL with well-defined interfaces, power/clock intent, and embedded assertions.
- Lead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with PD on floorplan and timing closure.
- Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.
- Architect and integrate high-performance interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and high-speed memory interfaces (HBM/DDR).
- Develop and enforce coding guidelines, reusable IP packaging, and signoff checklists.
What you'll need
- 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon.
- Proven track record of leading designs from spec → microarchitecture → RTL → signoff with strong PPA outcomes.
- Deep SystemVerilog RTL expertise, including clocking, resets, CDC/RDC handling, and protocol correctness.
- Extensive experience with front-end flows/tools (lint, CDC, synthesis/STA, DFT) using major EDA suites.
- Hands-on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, high-throughput datapaths.
- Strong cross-functional communication skills, capable of leading technical discussions and producing clear specifications.
Nice to have
- Background in AI/ML accelerator design.
- Formal verification/SVA expertise for property checking and design assertions.
- Experience with low-power design techniques (clock-/power-gating, UPF/CPF).
- Collaboration experience with cocotb/UVM for checkers and reference model co-development.
- Familiarity with RISC-V subsystems, coherence protocols, or customer-owned tooling (COT) flows.
Skills: microarchitecture, SystemVerilog RTL, PPA metrics, HBM/DDR, PCIe/CXL, AXI/ACE/CHI
This role has been open 0 days — well below the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
972
|
Median days open
63 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Positron AI | All employers we track in this specialty (972 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 972 |
| Open roles in the wider Digital Design & Verification family | 7 | 3097 · 114 employers |
| Median days open | 23 d | 63 d (−40 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Skills observed across this category: microarchitecture, SystemVerilog RTL, PPA metrics, HBM/DDR, PCIe/CXL, AXI/ACE/CHI
Who's hiring in this category
- Qualcomm · 147 open roles · median 48 d
- AMD · 66 open roles · median 65 d
- Synopsys · 59 open roles · median 20 d
- NXP Semiconductors · 53 open roles · median 70 d
- Analog Devices · 49 open roles · median 54 d
- NVIDIA · 48 open roles · median 48 d
How we counted: 972 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 24 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.