ASIC Design Engineer - Networking/ DPU/ AI Systems - CA, Santa Clara, United States
Originally posted 26 May 2026 by the employer. Relisted by the employer on 27 May 2026.
About the role
This role involves developing high-speed, complex ASICs from RTL architecture and design through tapeout, silicon bring-up, and mass production. You will join the NTSG team developing DPU ASICs and network processing engines for AI networking workloads.
What you'll do
- Architect and design key blocks for DPU ASICs targeting AI networking workloads, covering architecture definition, microarchitecture, and RTL design. - Collaborate on advanced network processing engines, including P4-based, protocol-independent packet processing solutions. - Design and implement high-speed ASIC blocks for networking and data movement applications. - Work closely with verification, modeling, software, and hardware teams to ensure functional correctness and system-level performance. - Debug and resolve issues across simulation, emulation, lab bring-up, and post-silicon phases while contributing to performance, power, and area optimization. - Support integration of ASIC IPs into larger SoC and system architectures.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - Seasoned ASIC design experience across the complete ASIC development cycle, from RTL architecture to tapeout to mass production. - Proven hands-on experience developing high-speed, complex ASICs with a solid background in networking and packet-processing architectures. - Strong RTL design skills in Verilog and SystemVerilog. - Strong programming skills in C/C++ and scripting experience in Python, Tcl, or Shell.
Nice to have
- Experience designing complex ARM- or RISC-V-based SoC ASICs. - Hands-on experience building complex Network-on-Chip (NoC) architectures and strong knowledge of AXI / AMBA protocols. - Familiarity with P4, programmable packet-processing pipelines, or protocol-independent networking architectures. - Experience with post-silicon debug, bring-up, and production support. - Experience with high-performance interconnect, data movement, and SoC integration.
Skills: SoC design, AI networking ASICs, chiplet based SoC architectures, RTL implementation, silicon bring up