ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal - San Jose, CA, United States
$150,000 - $250,000 USD yearly
Originally posted 20 February 2026 by the employer.
About the role
Celero is seeking an ASIC Design Engineer to design and implement digital circuits and mixed-signal ASICs for high-speed optical communication systems. The position focuses on developing and integrating DSP, digital communication, and high-speed SerDes functionality into complex ASICs.
What you'll do
- Design and implement digital circuits and ASIC blocks using Verilog and SystemVerilog. - Develop and integrate DSP, digital communication, and high-speed SerDes functionality into mixed-signal ASICs. - Perform synthesis, timing analysis, lint, formal equivalence, Clock Domain Crossing (CDC), and related ASIC implementation and signoff activities. - Optimize digital architectures for performance, power, and area (PPA). - Perform RTL simulation and debugging to ensure functionality and performance through block-level and top-level integration. - Develop automation scripts using Python, Tcl, or similar languages to support design and verification flows.
What you'll need
- Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related field. - 5+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems. - Strong proficiency in Verilog and/or SystemVerilog, alongside hands-on experience with industry-standard EDA tools. - Strong knowledge in at least one area among Digital Signal Processing (DSP), high-speed SerDes, Analog/Mixed-Signal ICs, digital communications, or optical communications. - Experience with DSP algorithms, data-path architectures, FEC, equalization, modulation/demodulation, or high-speed communication technologies. - Hands-on experience with synthesis, static timing analysis, Lint, CDC, formal verification, RTL simulation, and low-power design techniques.
Nice to have
- Experience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking. - Experience with coherent DSP, FEC, modulation schemes, equalization, or high-speed data recovery. - Experience with SerDes architectures, including TX/RX, CDR, PLLs, CTLE, DFE, ADC/DAC interfaces, or related high-speed mixed-signal circuitry. - Experience taking ASICs from architecture/RTL through synthesis, physical implementation, tapeout, and silicon bring-up. - Experience with MATLAB, Python, Tcl, or modeling and automation tools.
Skills: ASIC Design Engineer, digital circuits, HDL (Verilog/ System Verilog), synthesis, timing analysis, low-power design
This role has been open 200 days — well above the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1083
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Celero | All employers we track in this specialty (1083 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1083 |
| Open roles in the wider Digital Design & Verification family | 8 | 3310 · 115 employers |
| Median days open | 132 d | 64 d (+68 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC Design Engineer, digital circuits, HDL (Verilog/ System Verilog), synthesis, timing analysis, low-power design
Who's hiring in this category
- Qualcomm · 160 open roles · median 61 d
- Synopsys · 87 open roles · median 37 d
- AMD · 77 open roles · median 43 d
- Analog Devices · 49 open roles · median 54 d
- NXP Semiconductors · 42 open roles · median 93 d
- NVIDIA · 40 open roles · median 64 d
How we counted: 1083 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.