ASIC Design Engineer - CA, Santa Clara, United States
$116,000 - $218,500 USD yearly
Originally posted 15 July 2026 by the employer.
Work on GPU time distribution systems, engine schedulers, interrupt controllers, and copy engines.
About the role
As an ASIC Design Engineer, you will build SoC and GPU products across graphics, automotive, and artificial intelligence domains. You will work on IPs including GPU time distribution systems, engine schedulers, interrupt controllers, and copy engines.
What you'll do
- Draft microarchitecture documents and implement high-performance, area-, and power-efficient RTL to meet development targets and specifications. - Analyze architectural trade-offs based on features, performance requirements, and area/power constraints. - Implement microarchitecture in RTL and deliver verified, synthesis- and timing-clean builds. - Collaborate with architects, design engineers, and pre- and post-silicon verification teams. - Work on IP blocks including GPU time distribution systems, engine schedulers, interrupt controllers, and copy engines. - Assist the silicon bring-up team with debugging and post-silicon validation activities.
What you'll need
- BS or MS degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science. - 2+ years of relevant RTL design work experience. - Experience in micro-architecture, RTL development (Verilog), logic synthesis, power analysis, and timing analysis. - Understanding of digital systems, VLSI design, computer architecture, and computer arithmetic. - Scripting skills in Perl, Python, or industry-standard scripting languages.
Skills: micro-architecture, RTL, Verilog, logic synthesis, timing analysis, post-silicon validation
This role has been open 200 days — well above the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1083
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1083 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 36 | 1083 |
| Open roles in the wider Digital Design & Verification family | 229 | 3310 · 115 employers |
| Median days open | 50 d | 64 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: micro-architecture, RTL, Verilog, logic synthesis, timing analysis, post-silicon validation
Who's hiring in this category
- Qualcomm · 160 open roles · median 61 d
- Synopsys · 87 open roles · median 37 d
- AMD · 77 open roles · median 43 d
- Analog Devices · 49 open roles · median 54 d
- NXP Semiconductors · 42 open roles · median 93 d
- NVIDIA (this employer) · 40 open roles · median 64 d
How we counted: 1083 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.