ASIC Design Engineer, Architect-18711
Originally posted 1 November 2026 by the employer.
About the role
This role defines and develops ASIC RTL design and architecture across chip and block levels. Work centers on core IO protocols including DDR, PCIe, CXL, UAL (Universal Accelerator Link), and UCIe.
What you'll do
- Define and develop ASIC RTL design and verification at both chip and block levels.
- Create and execute design plans for complex digital designs, focusing on DDR, PCIe, CXL, UAL, and UCIe IO protocols.
- Collaborate with cross-functional teams to ensure seamless integration and functionality of designs.
- Utilize advanced design and verification methodologies and tools to achieve high-quality results.
- Mentor and guide junior engineers while promoting best practices.
- Communicate with internal and external stakeholders to align on project goals and deliverables.
What you'll need
- BSEE or BSCE with 12+ years of industry experience, or an advanced degree with 10+ years of industry experience.
- Extensive experience in ASIC RTL design.
- In-depth knowledge of DDR, PCIe, UAL, UCIe, and similar IO protocols and their applications.
- Proficiency in advanced digital design tools and methodologies.
Skills: ASIC, RTL, PCIe, CXL, UCIe, DDR
More semiconductor jobs: Synopsys jobs · SoC design jobs · Austin jobs
First seen in our index 0 days ago, well below the 82-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
486
|
Median days since first seen
82 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (486 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 486 |
| Open roles in the wider Digital Design & Verification family | 188 | 3533 · 119 employers |
| Median days since first seen | 11 d | 82 d (+71 d vs this employer) |
| Median salary (USD postings) | n/a | $230k |
Skills observed across this category: ASIC, RTL, PCIe, CXL, UCIe, DDR
Who's hiring in this category
- Qualcomm · 79 open roles · median 92 d
- NVIDIA · 67 open roles · median 84 d
- AMD · 39 open roles · median 71 d
- Arm Holdings · 29 open roles · median 14 d
- Apple · 28 open roles · median 15 d
- Micron Technology · 20 open roles · median 114 d
How we counted: 486 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.