ASIC Clocks Verification Engineer - New College Grad 2026 - CA, Santa Clara, United States
$116,000 - $189,750 USD yearly
Originally posted 9 October 2026 by the employer.
About the role
This role involves ASIC clocks verification, focusing on GPU clocking structures.
What you'll do
- Collaborate with architects, ASIC designers, and verification engineers to verify high-frequency clock structures.
- Engage with multiple teams to design GPU clock structures to satisfy architectural constraints.
- Deliver clock information to the SOC verification team, timing, and DFT teams.
- Use Perl to improve productivity for various teams.
- Collaborate with Software and product groups to debug GPU clock silicon bugs.
- Understand and design clocking structures to overcome sub-micron design challenges.
What you'll need
- Master’s degree in Electrical Engineering (or equivalent experience).
- Practical experience with SystemVerilog.
- Practical experience with Universal Verification Method (UVM).
- Experience with Design Verification.
- Experience with Logic Design.
- Experience with Logic Synthesis.
- Strong coding skills in Python, Perl, or other industry-standard scripting languages.
Skills: SystemVerilog, UVM, clock structures, ASIC verification, Perl
This role has been open 1 day — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1183
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1183 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 74 | 1183 |
| Open roles in the wider Digital Design & Verification family | 224 | 3171 · 114 employers |
| Median days open | 65 d | 64 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: SystemVerilog, UVM, clock structures, ASIC verification, Perl
Who's hiring in this category
- Qualcomm · 105 open roles · median 44 d
- AMD · 102 open roles · median 51 d
- NVIDIA (this employer) · 73 open roles · median 65 d
- Synopsys · 61 open roles · median 27 d
- SiFive · 54 open roles · median 68 d
- Cadence Design Systems · 51 open roles · median 110 d
How we counted: 1183 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.