ASIC Bench Characterization Manager (TERADYNE, Agoura Hills, CA)
$165,400 - $264,700 USD yearly
Originally posted 10 August 2026 by the employer.
About the role
This role involves leading the bench characterization team supporting new product development, combining people leadership with hands-on technical guidance. The position partners with ASIC design, ATE test, program/product management, and internal customers to deliver characterization results.
What you'll do
- Lead, coach, and develop a team of characterization engineers, including onboarding, feedback, prioritization, and career development.
- Partner with program/product management, ASIC design, ATE test, and internal customers to translate requirements into characterization execution plans.
- Guide bench-level test plans, PCB interface considerations, DUT communication, and automated measurement approaches.
- Review characterization data, correlate findings to system-level parameters, and ensure reports are ready for stakeholder review.
- Support complex bench-level debug, failure analysis, and failure-isolation activities.
- Communicate team progress, risks, and priorities to engineering leadership.
What you'll need
- Bachelor’s degree in Engineering or Physics.
- 10+ years of work experience in semiconductor characterization, bench measurements, or mixed-signal systems.
- Experience leading, mentoring, or managing engineers, or demonstrated readiness to grow into people leadership.
- Experience using benchtop equipment such as power supplies, SMUs, semiconductor parameter analyzers, multimeters, signal generators, AWGs, pattern generators, BERTs, oscilloscopes, VNAs, and spectrum analyzers.
- Programming experience; VBA preferred, with additional knowledge of Python, MATLAB, or C++.
- Experience programming in Verilog and working with SCPI communication.
- Experience with revision control; Git preferred.
- Strong cross-functional communication skills.
Nice to have
- Electrical/Computer Engineering degree preferred.
- Experience with mixed-signal (analog and digital) systems, multi-GHz signal delivery, de-embedding, and signal/power integrity.
- Experience characterizing PLLs, jitter, data eyes, DACs, and ADCs.
Skills: bench characterization, semiconductor characterization, bench measurements, mixed-signal systems, benchtop equipment, debug
This role has been open 68 days — well above the 42-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
409
|
Median days open
42 d
|
Median salary
$167k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (409 roles · 61 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 409 |
| Open roles in the wider Silicon Validation & Test family | 92 | 2218 · 113 employers |
| Median days open | 68 d | 42 d (+26 d vs this employer) |
| Median salary (USD postings) | — | $167k |
Skills observed across this category: bench characterization, semiconductor characterization, bench measurements, mixed-signal systems, benchtop equipment, debug
Who's hiring in this category
- AMD · 58 open roles · median 43 d
- Micron Technology · 39 open roles · median 39 d
- Qualcomm · 36 open roles · median 28 d
- NVIDIA · 26 open roles · median 23 d
- Microchip Technology · 22 open roles · median 68 d
- Graphcore · 20 open roles · median 121 d
How we counted: 409 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.