Architect Digital Design -High Speed Memory Interface IP- HBM/DDR/LPDDR

Originally posted 13 September 2026 by the employer.

Define the architecture for HBM, DDR, or LPDDR memory controllers.

About the role

This role defines and owns the digital architecture for HBM, DDR, or LPDDR memory controllers, spanning from high-level partitioning to RTL implementation strategy. The designs will power AI accelerators, data center processors, and mobile SoCs, with a focus on HBM, DDR, and LPDDR digital core protocols.

What you'll do

• Define and own the digital architecture for HBM, DDR, or LPDDR memory controllers, from high-level partitioning through RTL implementation strategy
• Drive design plans for complex memory interface blocks, balancing performance, area, power, and verification complexity
• Collaborate with PHY teams, verification engineers, and product architects to ensure seamless integration and protocol compliance
• Evaluate and select design methodologies, tools, and flows that improve quality and reduce cycle time
• Mentor engineers on architecture decisions, RTL best practices, and debug strategies for high-speed memory interfaces
• Work with customers and internal stakeholders to align on feature requirements, timing constraints, and delivery milestones

What you'll need

• 12 - 15+ years of hands-on experience in ASIC digital design, with significant time spent on memory interfaces or high-speed IO protocols
• Deep technical knowledge of at least one of HBM, DDR, LPDDR, or similar memory protocols, including controller architecture, training, and PHY interface
• Proven ability to define and execute complex digital architectures from concept through RTL implementation and silicon bring-up
• Strong understanding of AMBA or similar on-chip interconnect protocols and how memory controllers integrate into SoC architectures
• Experience with advanced digital design tools and methodologies, including synthesis, timing closure, and low-power design techniques