Applications Engineering, Staff Engineer
Originally posted 19 October 2026 by the employer.
Support customer engagements on advanced-node physical design implementations using Fusion Compiler and ICC2.
About the role
As a Staff Applications Engineer at Synopsys, you will support customer engagements on physical design implementations across the RTL-to-GDS flow. You will focus on advanced-node designs at 7nm, 5nm, and below using Fusion Compiler and ICC2 to meet PPA targets under tight tape-out timelines.
What you'll do
- Support customer engagements on advanced-node designs at 7nm, 5nm, and below using Fusion Compiler and ICC2 to achieve PPA targets. - Develop and enhance physical design methodologies and automation solutions using TCL, Python, and Perl across the RTL-to-GDS flow. - Debug physical design challenges including placement, clock tree synthesis, routing, timing closure, and power optimization on FinFET designs with multi-patterning and electromigration constraints. - Build and deliver tailored methodology recommendations based on customer design constraints, process technologies, and project schedules. - Contribute to AI-assisted and machine learning-driven design optimization initiatives using data-driven approaches. - Collaborate with R&D, product management, and field teams to translate customer challenges into tool requirements and feature enhancements.
What you'll need
- Bachelor's degree in electrical engineering or a related field with 5+ years of hands-on ASIC physical design experience, or a master's degree with 3+ years of experience. - Proficiency with implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus on tapeouts. - Scripting and automation skills using TCL, Python, or Perl to build flows and analyze data. - Understanding of advanced-node design challenges at 7nm and below, including FinFET effects, multi-patterning, and electromigration. - Experience with logical and physical synthesis flows. - Willingness to travel to customer sites as needed to provide onsite support during critical design phases.
Skills: physical design, ICC2, Fusion Compiler, Tcl, timing closure