Applications Engineering, Sr. Staff Engineer
Originally posted 16 September 2026 by the employer — open 2 days.
About the role
This Applications Engineering, Sr. Staff Engineer role involves providing technical support and guidance to semiconductor customers using Synopsys physical design tools.
What you'll do
- Support pre-sales and post-sales engagements, demonstrating Synopsys physical design tools including Fusion Compiler and ICC2 in live technical sessions.
- Debug complex physical design issues across the RTL-to-GDSII flow, resolving placement, routing, timing closure, and congestion challenges at advanced nodes.
- Develop and deliver technical methodologies for clock tree synthesis, AI-driven optimization, macro placement, and timing closure.
- Build proof-of-concept designs and benchmarks showing PPA improvements using Synopsys tools.
- Collaborate with product engineering teams to translate customer pain points into feature requests and tool enhancements.
- Train customer engineers on advanced Synopsys tool capabilities, including multi-scenario optimization and noise-aware routing techniques.
What you'll need
- Bachelor's degree in Electrical Engineering or equivalent with 9+ years of hands-on ASIC physical design experience, or Master's degree with 7+ years.
- Deep expertise in RTL-to-GDSII flows using industry-standard tools, with direct experience in placement, optimization, clock tree synthesis, and routing.
- Hands-on proficiency with Synopsys backend tools including Fusion Compiler, ICC2, Design Compiler, and PrimeTime.
- Strong understanding of advanced node design challenges (7nm and below), including FinFET effects, multi-patterning constraints, and electromigration.
- Experience with timing closure techniques, multi-scenario optimization, and noise analysis in complex SoC designs.
- Willingness to travel up to 30% to customer sites for technical engagements and on-site support.
Skills: physical design tools, RTL-to-GDSII flow, placement, routing, timing closure
This role has been open 0 days — well below the 86-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
680
|
Median days open
86 d
|
Median salary
$197k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (680 roles · 73 employers) |
|---|---|---|
| Open roles in this specialty | 55 | 680 |
| Open roles in the wider Physical Implementation family | 87 | 1379 · 105 employers |
| Median days open | 57 d | 86 d (−29 d vs this employer) |
| Median salary (USD postings) | — | $197k |
Skills observed across this category: physical design tools, RTL-to-GDSII flow, placement, routing, timing closure
Who's hiring in this category
- Cadence Design Systems · 173 open roles · median 141 d
- Synopsys (this employer) · 52 open roles · median 58 d
- NVIDIA · 50 open roles · median 90 d
- Micron Technology · 36 open roles · median 119 d
- Qualcomm · 36 open roles · median 72 d
- Intel Corporation · 29 open roles · median 23 d
How we counted: 680 open EDA/CAD Engineering (EDA Tools) roles from 73 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.