Applications Engineer, Senior Engineer
Synopsys
img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Austin, Texas, United States
4 days ago
Applications & FAE
Originally posted 11 October 2026 by the employer.
About the role
This role involves leading VCS simulation deployments at customer sites, focusing on integrating the tool into existing flows and resolving adoption blockers. You will work with a deep technical understanding of verification and debug solutions to ensure successful chip tape-outs.
What you'll do
- Lead VCS simulation deployments at customer sites, integrating the tool into existing flows.
- Diagnose complex simulation mismatches, performance bottlenecks, and verification environment issues using VCS, Verdi, and related debugging infrastructure.
- Partner with field application engineers and R&D to translate customer pain points into actionable product requirements.
- Drive competitive evaluations and benchmarking engagements, demonstrating VCS capabilities.
- Develop automation scripts in Perl, TCL, Shell, and Make to streamline customer workflows.
- Support customers using advanced verification methodologies including UVM, SVA, low-power simulation, gate-level verification, and functional safety flows.
What you'll need
- Bachelor's in Electronics or Computer Engineering with 5+ years of experience, or Master's with 3+ years, focused on digital design verification.
- Deep hands-on experience with simulation technologies, including VCS or equivalent commercial simulators, and strong understanding of event-driven simulation internals.
- Proficiency in SystemVerilog, UVM, SVA, and HDL languages like Verilog and VHDL.
- Proven track record debugging simulation mismatches, performance issues, and verification flow problems.
- Strong scripting skills in Perl, TCL, Shell, and Make.
- Working knowledge of UNIX/Linux environments, version control systems, and large-scale verification infrastructure.
- Experience with Synopsys tools like Verdi, exposure to low-power simulation, gate-level verification, and functional safety methodologies is a strong plus.
Skills: VCS simulation, UVM, SystemVerilog, verification flow, debug
Synopsys
img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Austin, Texas, United States
On-site
4 days ago