Applications Engineer, Lead - Allen, TX / Boise, ID, United States
Originally posted 25 June 2026 by the employer.
Synopsys CATS, NCS NDE, GDSII/OASIS, and Mask Proximity Correction (MPC) for photomask data preparation.
About the role
This role evaluates and supports digital integrated-circuit processing and MES requirements for mask manufacturing. The Applications Engineer lead defines data-operation workflows, analyzes software solutions, and works with vendors, customers, and internal teams to implement mask data capabilities.
What you'll do
- Define technical standards and workflows for photomask data preparation across the regional data engineering organization. - Prepare and optimize mask data using tools such as Synopsys CATS and NCS NDE, converting layout files in GDSII/OASIS formats into fractured, production-ready mask data. - Generate job decks, manage reticle layout and frame placement, and support metrology activities. - Conduct layout verification using Mask Rule Checks (MRC) and Mask Proximity Correction (MPC) to ensure manufacturability and design integrity. - Perform root cause analysis and resolution of complex layout or data issues across manufacturing, design, and customer teams. - Lead evaluations of new data operation tools and methodologies while partnering with corporate teams to implement automation solutions.
What you'll need
- 6 to 8+ years of experience in photomask data preparation, IC layout/data engineering, or related semiconductor design disciplines. - Expert knowledge of GDSII/OASIS formats, data hierarchies, and semiconductor layout principles. - Strong Unix environment experience and proven ability to work on-site at Boise, ID or Allen, TX. - Bachelor's degree (or equivalent work experience) in Electrical Engineering, Computer Engineering, or a related technical field. - Ability to obtain US government clearance.
Nice to have
- Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
Skills: photomask data preparation, GDSII/OASIS, layout verification, MRC, MPC
This role has been open 119 days — well above the 72-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
683
|
Median days open
72 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Photronics | All employers we track in this specialty (683 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 683 |
| Open roles in the wider Physical Implementation family | 1 | 1489 · 110 employers |
| Median days open | 119 d | 72 d (+47 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: photomask data preparation, GDSII/OASIS, layout verification, MRC, MPC
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 149 d
- Synopsys · 62 open roles · median 40 d
- Micron Technology · 46 open roles · median 49 d
- Qualcomm · 37 open roles · median 73 d
- GlobalFoundries · 36 open roles · median 28 d
- Keysight Technologies · 34 open roles · median 76 d
How we counted: 683 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.