Analog Mixed Signal Circuit Design - San Jose (Holger Way), United States
$191,500 - $263,300 USD yearly
Originally posted 17 July 2026 by the employer — open 55 days.
About the role
This role is for a Principal Circuit Designer to design and deliver high-speed, high-linearity analog and SERDES circuit blocks that form the Analog Front End (AFE) of automotive transceivers. This is an individual contributor role with a focus on TX, RX, and clocking circuit design for high-speed PHYs.
What you'll do
- Architect, design, and simulate analog circuit blocks including TX, RX, and clocking circuits.
- Translate system- and PHY-level requirements into robust block-level specifications.
- Optimize designs for linearity, noise, jitter, power, area, and robustness.
- Perform detailed transistor-level simulations across PVT corners and automotive temperature ranges.
- Support silicon bring-up, characterization, and validation of analog/SERDES blocks.
- Correlate simulation results with silicon measurements and drive design improvements.
- Drive resolution of performance, yield, and reliability issues through root-cause analysis.
- Serve as block-level technical owner for critical analog/SERDES functions.
- Participate in and lead technical design reviews.
- Mentor senior and mid-level designers and contribute to design best practices.
What you'll need
- MSEE or PhD in Electrical Engineering.
- 12-15+ years of experience in analog or mixed-signal IC design.
- Proven hands-on experience designing high-speed SERDES or wireline analog circuits.
- Demonstrated success delivering TX, RX, and clocking circuits to production silicon.
- Extensive experience with circuit design, simulation, and debug at the transistor level.
- Expertise in high-speed TX and RX circuit design.
- Expertise in linearity, distortion, and noise analysis.
- Expertise in jitter generation, tolerance, and clock integrity.
- Expertise in PLL / DLL and clocking architectures.
- Expertise in PVT variation and automotive robustness.
- Expertise in advanced CMOS processes for high-speed analog.
Nice to have
- Direct experience with 10GBASE-T, 10GBASE-T1 (Automotive Ethernet), or TDD-based transceivers.
- Familiarity with automotive semiconductor requirements (AEC-Q100, temperature, EMI/EMC).
- Experience supporting automotive production ramp and customer qualification.
- Exposure to ISO 26262 / functional safety concepts.
Skills: Analog/SERDES Circuit Design, TX/RX circuits, PLLs, jitter, transistor-level simulations, silicon validation
This role has been open 176 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 3 | 217 |
| Median days open | 79 d | 91 d (−12 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Analog/SERDES Circuit Design, TX/RX circuits, PLLs, jitter, transistor-level simulations, silicon validation
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.