Analog Layout Principal Engineer - Bangalore, India
Originally posted 9 October 2026 by the employer.
About the role
This role involves the design and development of complex analog, mixed-signal, and custom layouts within the Central Engineering business group.
What you'll do
- Design and develop complex analog, mixed-signal, and custom layouts using Cadence Virtuoso and similar EDA tools across deep sub-micron, FinFET, and GAA nodes.
- Drive end-to-end physical verification closure, resolving DRC, LVS, ERC, and antenna violations within project timelines.
- Own layout planning from floor planning to final tapeout, including layout architecture, shielding, isolation, EM/IR optimization, and parasitic management.
- Coordinate across design, verification, package, and physical implementation teams and support tapeout activities.
- Lead technical discussions, layout reviews, and serve as the technical focal point for domain expertise within the team.
- Own cluster, including high-level integration and top-level layout decisions, and provide critical layout feedback.
What you'll need
- Bachelor's or master's degree in Electronics & Communication, Electrical & Electronics, or a related field.
- 15+ years of experience in high-speed analog, mixed-signal, and custom layout design across multiple projects and technology nodes.
- Deep understanding of electrical engineering fundamentals and layout behavior across advanced nodes, including FinFET.
- Expert-level proficiency in EDA tools and proven experience handling complex and critical IPs with end-to-end ownership.
- Expertise in critical layout techniques such as device matching, signal flow optimization, clock routing, shielding, parasitic minimization, biasing, and robust power routing.
- Solid understanding of reliability considerations including EM/IR, latch-up prevention, ESD protection, and power planning.
Skills: Cadence Virtuoso, DRC, LVS, FinFET, tapeout
This role has been open 18 days — well below the 35-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
75
|
Median days open
35 d
|
Median salary
$164k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (75 roles · 24 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 75 |
| Open roles in the wider Analog & Mixed-Signal family | 29 | 1461 · 106 employers |
| Median days open | 31 d | 35 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $164k |
Skills observed across this category: Cadence Virtuoso, DRC, LVS, FinFET, tapeout
Who's hiring in this category
- Analog Devices · 9 open roles · median 35 d
- Celero · 8 open roles · median 59 d
- Renesas Electronics · 7 open roles · median 24 d
- Marvell Technology (this employer) · 6 open roles · median 31 d
- onsemi · 6 open roles · median 27 d
- Infineon Technologies · 5 open roles · median 12 d
How we counted: 75 open Analog IC Design (Analog Layout) roles from 24 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.