Analog Layout Lead - San Jose, United States
Originally posted 2 September 2026 by the employer — open 7 days.
About the role
What you'll do
- Lead full-custom layout of complex analog and mixed-signal blocks, including PLLs, ADCs, DACs, LDOs, bandgaps, and high-speed I/O.
- Define and enforce analog layout methodologies, design rules, and best practices across the physical design team.
- Drive parasitic-aware layout strategies to meet stringent noise, matching, signal integrity, and power requirements.
- Collaborate with circuit designers to translate schematic intent into optimized physical implementations.
- Own physical verification closure, including DRC, LVS, and antenna checks, across advanced process nodes.
- Provide technical guidance and layout direction to engineers and contractors, reviewing layouts and driving consistency.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or relevant technical field.
- 8+ years of experience in full-custom analog and mixed-signal layout for production silicon in advanced CMOS process nodes.
- 8+ years of hands-on experience with industry-standard layout tools such as Cadence Virtuoso for schematic-driven layout, parasitic extraction, and physical verification.
- Experience leading layout of high-performance analog blocks such as PLLs, voltage regulators, data converters, or high-speed interfaces from concept through tape-out.
- Experience defining and implementing layout methodologies for matching, shielding, noise isolation, and signal integrity in mixed-signal environments.
- Experience managing, mentoring, and reviewing the work of layout engineers and coordinating deliverables with external contractors.
Nice to have
- Familiarity with post-layout simulation flows, including RC extraction and back-annotated verification using tools such as Spectre or Calibre.
- Experience contributing to or evaluating process design kits and design rule documentation for new process node bring-up.
- Experience with analog layout for photonics, AI infrastructure, consumer wearable, mobile, or IoT SoCs where power, area, and reliability constraints are critical.
- Experience with 3D stacking technologies, advanced packaging layout considerations, or reusable analog layout templates.
Skills: full-custom layout, Cadence Virtuoso, DRC LVS, parasitic extraction, PLLs ADCs DACs LDOs
This role has been open 7 days — well below the 66-day median for Analog IC Design roles.
Analog IC Design · Analog Design
|
Open roles in category
259
|
Median days open
66 d
|
Median salary
$156k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lumilens | All employers we track in this specialty (259 roles · 46 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 259 |
| Open roles in the wider Analog & Mixed-Signal family | 5 | 1317 · 100 employers |
| Median days open | 7 d | 66 d (−59 d vs this employer) |
| Median salary (USD postings) | — | $156k |
Skills observed across this category: full-custom layout, Cadence Virtuoso, DRC LVS, parasitic extraction, PLLs ADCs DACs LDOs
Who's hiring in this category
- Micron Technology · 33 open roles · median 45 d
- Texas Instruments · 30 open roles · median 111 d
- NXP Semiconductors · 15 open roles · median 65 d
- Renesas Electronics · 14 open roles · median 53 d
- onsemi · 13 open roles · median 111 d
- Semtech · 11 open roles · median 83 d
How we counted: 259 open Analog IC Design (Analog Design) roles from 46 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.