Analog Layout Intern, BS - Summer 2027 - United States
Originally posted 22 September 2026 by the employer.
About the role
This role is for an Analog Layout Engineer Intern, focusing on providing IP to various business units including Automotive, Storage, Security, and Networking. You will contribute to the development of semiconductor IP across advanced process nodes.
What you'll do
- Translate analog IC schematics into physical layout using Cadence Virtuoso.
- Run design rule checks (DRC), layout versus schematic (LVS), and other physical verification flows.
- Collaborate with Analog IC Designers to refine, debug, and iterate on layouts.
- Present progress updates and technical findings in team meetings and project reviews.
- Contribute to the development of semiconductor IP across advanced process nodes.
What you'll need
- Currently pursuing a Bachelor's Electrical Engineering, Computer Engineering, or a related field with an expected graduation date between Fall 2027 – Summer 2028.
- Fundamental understanding of electrical engineering concepts, including analog circuit theory and microelectronics.
- Coursework or hands-on experience in analog design, IC layout, or VLSI design.
- Familiarity with CAD tools used for physical IC design (e.g., Cadence Virtuoso, Calibre, or similar EDA tools).
Skills: Analog Layout Engineer, Cadence Virtuoso, DRC, LVS, physical IC design, advanced process nodes
This role has been open 0 days — well below the 18-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
38
|
Median days open
18 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (38 roles · 22 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 38 |
| Open roles in the wider Analog & Mixed-Signal family | 13 | 1339 · 106 employers |
| Median days open | 13 d | 18 d (−5 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: Analog Layout Engineer, Cadence Virtuoso, DRC, LVS, physical IC design, advanced process nodes
Who's hiring in this category
- Analog Devices · 4 open roles · median 6 d
- Celero · 4 open roles · median 13 d
- Marvell Technology (this employer) · 3 open roles · median 17 d
- QORVO · 3 open roles · median 25 d
- Renesas Electronics · 3 open roles · median 6 d
- Infineon Technologies · 2 open roles · median 34 d
How we counted: 38 open Analog IC Design (Analog Layout) roles from 22 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.