Analog Layout Automation Engineer - Austin, United States
Originally posted 2 October 2026 by the employer.
This role focuses on SerDes, PLLs, and sensors within Apple's SOCs.
About the role
As an Analog Layout Automation Engineer, you will contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors. This role leverages AI/ML techniques for improved design and efficiency within Apple's multi-billion transistor SOCs.
What you'll do
- Convert design concepts into silicon by collaborating with circuit designers and using advanced CAD tools.
- Review floor plans, analyze circuits, run verification suites, and resolve LVS/DRC/ERC issues.
- Drive automation by developing scripts and improving workflows.
- Apply AI/ML for layout optimization, verification acceleration, and advanced modeling.
- Implement intelligent quality metrics, reduce manual effort, and generate data-driven design insights.
What you'll need
- BS and a minimum of 10 years relevant industry experience.
- Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies.
- Strong programming/scripting skills in SKILL, Perl, TCL, Shell, and/or Python.
- Solid understanding of supervised and self-supervised learning, convolutional neural networks (CNNs), loss functions, backpropagation, and optimization.
- Hands-on experience with PyTorch for model development and experimentation.
- Demonstrated ability to automate layout tasks, flows, and quality checks using scripting and CAD tools.
- Proven record in implementing high-quality analog layouts with tight device matching, low noise, and low power consumption.
- Familiarity with failure-prone circuit/layout structures, analog and DFM best practices, and the ability to diagnose and resolve layout-related issues.
- Strong proficiency in custom and standard-cell floor planning, hierarchical layout assembly, and physical integration.
- Understanding of image processing fundamentals, spatial representations, multi-channel image handling, segmentation, and object detection concepts.
- Technical understanding of IR drop, RC delay, electromigration, self-heating, coupling capacitance, and related reliability concerns.
- High proficiency in interpreting physical verification reports, including DRC, ERC, and LVS.
- Experience using advanced Cadence Virtuoso features (XL, EAD, APR, Constraint Manager).
- Familiarity with Cadence Innovus.
- Experience with CAD automation workflows and PCell creation.
Skills: analog layout automation, SKILL, Perl, TCL, Python, Cadence Virtuoso, DRC, LVS
This role has been open 7 days — well below the 79-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
704
|
Median days open
79 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (704 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 704 |
| Open roles in the wider Physical Implementation family | 36 | 1485 · 107 employers |
| Median days open | 10 d | 79 d (−69 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: analog layout automation, SKILL, Perl, TCL, Python, Cadence Virtuoso
Who's hiring in this category
- Cadence Design Systems · 163 open roles · median 162 d
- Synopsys · 59 open roles · median 36 d
- Micron Technology · 44 open roles · median 107 d
- Qualcomm · 42 open roles · median 60 d
- NVIDIA · 41 open roles · median 73 d
- GlobalFoundries · 30 open roles · median 51 d
How we counted: 704 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.