Analog Design, Sr Staff Engineer
Originally posted 18 August 2026 by the employer.
Work on SerDes IP that ships in AI accelerators, data center switches, automotive SoCs, and consumer electronics.
About the role
This role involves designing and optimizing analog front-end building blocks for SerDes IP.
What you'll do
- Design and optimize analog front-end building blocks for SerDes IP, including voltage and current-mode drivers, equalizers (CTLE, FFE, DFE), CDR circuits, PLLs, DLLs, VCOs, phase interpolators, bandgaps, and regulators.
- Run SPICE simulations across PVT corners and create verification test benches that validate performance against PCIe 6.0, PCIe 7.0, PAM4, Ethernet, USB, HDMI, or other high-speed protocol specifications.
- Collaborate closely with layout engineers to minimize parasitic resistance and capacitance, reduce mismatch, and account for proximity effects in sub-micron CMOS processes.
- Work with digital RTL engineers to verify calibration loops, adaptation algorithms, and control logic that tune analog circuits in real time.
- Present simulation results, design tradeoffs, and performance data in peer reviews and customer-facing technical discussions.
- Document circuit architecture, design features, verification strategies, and test plans for integration into larger SerDes products.
- Own the full lifecycle of blocks from spec to silicon, including post-layout verification, characterization support, and design-for-reliability checks for electromigration, IR drop, aging, and ESD.
What you'll need
- PhD with 2+ years of hands-on SerDes or high-speed analog design experience, or BTech/MTech with 5 to 10 years in the same domain.
- Silicon-proven experience designing and bringing up analog or mixed-signal blocks in production chips.
- Deep expertise in at least several of these building blocks: analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, VCOs, CDR circuits, bandgaps, regulators, CTLE, FFE, DFE, impedance calibrators, serializers, deserializers, or phase interpolators.
- Strong proficiency with SPICE simulation tools and sub-micron CMOS design methodologies.
- Experience optimizing layout for performance, including parasitic extraction, device matching, stress effects, and design-for-reliability considerations like electromigration, IR drop, and aging.
Skills: SerDes IP, voltage-mode drivers, PLLs, equalizers, CDR circuits
This role has been open 41 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 26 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 36 | 1385 · 107 employers |
| Median days open | 44 d | 76 d (−32 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: SerDes IP, voltage-mode drivers, PLLs, equalizers, CDR circuits
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys (this employer) · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.