Analog Design, Sr Staff Engineer
Originally posted 28 July 2026 by the employer.
This role focuses on high-speed SerDes products.
About the role
This role involves the design and development of analog circuits for high-speed SerDes products, ensuring their reliability and performance. The team is dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes.
What you'll do
- Drive the design and development of analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards.
- Guide analog designers to ensure designs meet electrical specifications and reliability constraints.
- Define methods and procedures for project execution, including planning analog design activities and associated milestones.
- Conduct and prepare design reviews, following up on improvements, and ensuring high quality outcomes.
- Evaluate and minimize parasitic effects related to layout implementations, collaborating with layout teams to optimize performance, power, and area.
- Ensure silicon correlation with simulation results, validating design accuracy and robustness.
- Mentor and train less experienced analog designers, fostering skill development within the team.
What you'll need
- M.Sc. in Electrical Engineering with 8+ years of experience, or Ph.D. in Electrical Engineering with 6+ years of experience.
- Proven track record in CMOS analog design, preferably including hands-on experience with ADC, DAC, PLL, Rx, Tx, References.
- Experience coordinating design activities across teams and managing medium complexity designs.
- Familiarity with industry-standard IC design packages and EDA tools.
- Experience working in UNIX operating systems.
- Strong written and verbal communication skills in English.
Nice to have
- System-level knowledge of SerDes architecture.
Skills: high-speed SerDes products, Ethernet and PCIe standards, CMOS analog design, ADC, DAC, PLL, Rx, Tx, FinFET/GAA process nodes, silicon correlation
This role has been open 62 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 28 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 38 | 1385 · 108 employers |
| Median days open | 32 d | 76 d (−44 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: high-speed SerDes products, Ethernet and PCIe standards, CMOS analog design, ADC, DAC, PLL, Rx, Tx, FinFET/GAA process nodes, silicon correlation
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys (this employer) · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.