Originally posted 31 May 2026 by the employer — open 102 days.

About the role

This role involves owning physical layout for high-speed analog and mixed signal IP blocks. The focus is on SerDes and high-speed analog IP blocks.

What you'll do

Design and own physical layout for high-speed analog and mixed signal IP blocks including SerDes, PLLs, TX/RX circuits, and custom digital logic paths.
Perform full layout verification flow including DRC, LVS, LPE using Calibre, ICV, and STAR-RXCT.
Collaborate with analog circuit designers to translate schematics into optimized layouts.
Apply advanced floorplanning techniques to manage signal integrity, power distribution, EM/IR constraints, and ESD/latchup mitigation in deep submicron and FinFET processes.
Generate LEFs and support top-level integration into larger SoC designs.
Debug complex layout issues using parasitic extraction, simulation correlation, and hands-on troubleshooting.
Drive layout automation through scripting to improve turnaround time and consistency.

Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering.
6+ years of hands-on experience in analog and mixed signal custom IC layout, with specific exposure to high-speed analog circuits.
Proven experience with Custom Designer or Cadence Virtuoso for layout design.
Strong working knowledge of Calibre, ICV, and STAR-RXCT for DRC, LVS, and parasitic extraction.
Solid understanding of CMOS and FinFET layout techniques, deep submicron effects, and mitigation strategies.
Experience with layout verification flow including LEF generation, top-level integration, EM/IR analysis, and DFM considerations.

Skills: analog layout, mixed signal layout, SerDes, FinFET, DRC LVS, Cadence Virtuoso