Analog Design, Sr Architect - 18618
Originally posted 3 November 2026 by the employer.
About the role
Synopsys is seeking an Analog Design Senior Architect to own macro-level architecture, design, and implementation of critical analog circuits for SerDes IP across TX, RX, and clock paths. The role translates SerDes standards and system architecture into circuit platforms and layout implementations reusable across product variants and process nodes.
What you'll do
- Own macro-level architecture and circuit design for SerDes IP across TX, RX, and clock paths, defining budgets for jitter, noise, linearity, settling, latency, power, and area.
- Define interfaces between analog macros and digital calibration, adaptation, and control, collaborating with RTL and firmware teams on algorithms and observability hooks.
- Establish verification strategies using SPICE simulation for corner and Monte Carlo analysis, aging, mismatch, noise, transient jitter, PVT sweeps, and reliability checks.
- Build Verilog-A behavioral models to support system validation and correlation between block-level and top-level simulation results.
- Guide FinFET layout implementations to mitigate parasitics, coupling, device stress, EM and IR drop, and local mismatch while addressing ESD and high-speed interconnect integrity.
- Drive silicon correlation plans by defining critical laboratory measurements, mapping results back to simulations, and consulting on electrical characterization and DFT hooks.
What you'll need
- PhD with 10+ years or MSc with 12+ years of SerDes or high-speed analog design experience with multiple silicon successes.
- Demonstrated experience delivering complex analog IP through tapeout and silicon validation at the macro architecture level.
- Deep transistor-level design expertise in CMOS and FinFET processes, including proven circuit implementations for SerDes TX, RX, and clock paths.
- In-depth design knowledge of SerDes sub-circuits, including equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.
- Hands-on proficiency with SPICE simulators and EDA tools for schematic entry, physical layout, and design verification.
- Experience with analog behavioral modeling in Verilog-A and scripting in TCL, Perl, C, Python, or MATLAB for design automation and data analysis.
Skills: SerDes, analog design, FinFET, equalizer, PLL
More semiconductor jobs: Synopsys jobs · Signal integrity jobs · Sunnyvale jobs
This role has been open 0 days — well below the 78-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
249
|
Median days open
78 d
|
Category median salary (all employers)
$207k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (249 roles · 50 employers) |
|---|---|---|
| Open roles in this specialty | 34 | 249 |
| Open roles in the wider Analog & Mixed-Signal family | 55 | 1527 · 111 employers |
| Median days open | 37 d | 78 d (−41 d vs this employer) |
| Median salary (USD postings) | — | $207k |
Skills observed across this category: SerDes, analog design, FinFET, equalizer, PLL
Who's hiring in this category
- Synopsys (this employer) · 34 open roles · median 39 d
- AMD · 24 open roles · median 45 d
- Cadence Design Systems · 21 open roles · median 149 d
- Qualcomm · 17 open roles · median 83 d
- NVIDIA · 16 open roles · median 210 d
- Micron Technology · 10 open roles · median 49 d
How we counted: 249 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 50 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.