Analog Design, Principal Engineer
Originally posted 15 February 2026 by the employer — open 207 days.
About the role
This role involves leading NRZ/PAM4 Serdes analog design transceiver solutions and developing Analog Full custom circuit macros for High Speed PHY IP.
What you'll do
- Lead NRZ/PAM4 Serdes analog design transceiver solutions.
- Develop Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes.
- Collaborate with silicon test and debug experts for Sim2Sil correlation.
- Analyze mixed signal techniques for power reduction, performance enhancement, and area reduction.
What you'll need
- 15+ years of relevant experience (BE) or 12+ years (MTech) in mixed signal analog, clock, and datapath circuit design.
- Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.
- Knowledge in Equalizers, CDR architectures, high-speed digital circuit design, timing/phase noise analysis, and signal integrity.
- Knowledge of RF architecture and blocks such as transceivers front-end, VCOs, LNA, and up/down converters.
- Strong fundamentals of CMOS, device physics, and sub-micron design methodologies.
- Experience with PLL designs and high-speed digital circuit design.
- Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques.
- Familiarity with digitally assisted analog circuit techniques.
Skills: Serdes analog design, High Speed PHY IP, PLLs, data converters, FinFet, NRZ/PAM4
This role has been open 119 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 16 | 217 |
| Median days open | 53 d | 91 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Serdes analog design, High Speed PHY IP, PLLs, data converters, FinFet, NRZ/PAM4
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys (this employer) · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.