$104,100 - $166,600 USD yearly
Originally posted 4 November 2026 by the employer.
About the role
Teradyne’s Semiconductor Test Division is seeking an Analog Design Engineer to contribute to the development of high-speed analog and mixed-signal ASICs for Automatic Test Equipment (ATE).
What you'll do
- Design, simulate, and optimize high-speed analog and mixed-signal circuits from specification through transistor-level implementation.
- Perform circuit-level verification and simulation across process, voltage, and temperature (PVT) corners using Cadence EDA tools.
- Support schematic, layout, physical verification, and ASIC integration activities in collaboration with other members of the design team.
- Support silicon characterization, laboratory measurements, debug, validation, and production test activities.
- Develop and maintain scripts and automation tools in Python, SKILL, or Ocean to improve simulation, verification, characterization, and data analysis workflows.
- Explore the use of AI-assisted engineering tools and methodologies to improve design productivity and analysis.
What you'll need
- Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline, with 2+ years of relevant industry experience in analog or mixed-signal IC design, simulation, or characterization.
- Hands-on experience with CMOS analog or mixed-signal circuit design and simulation.
- Working knowledge of common analog and mixed-signal circuit architectures (e.g., PLLs, DLLs, ADCs, DACs, VCOs, CDRs, amplifiers, clocking circuits, high-speed I/Os, or CML circuits).
- Understanding of CMOS device fundamentals, semiconductor processes, PDKs, and PVT effects.
- Experience with industry-standard IC design and simulation tools, preferably Cadence.
- Experience with scripting or programming languages such as Python, SKILL, or Ocean for engineering automation or data analysis.
Nice to have
- Experience supporting one or more ASICs through tape-out, silicon bring-up, characterization, or production test.
- Familiarity with advanced semiconductor technologies, including FinFET processes at 16nm or below.
- Exposure to high-frequency or high-speed analog and mixed-signal design.
- Experience with laboratory characterization and test equipment.
- Familiarity with Verilog or Verilog-A.
- Exposure to AI/ML, generative AI, or large-scale data analysis applied to semiconductor design, verification, validation, or test.
Skills: CMOS, Cadence, Transistor-level, Analog IC, PVT Simulation
More semiconductor jobs: Teradyne jobs · Analog design jobs · California jobs
First seen in our index 9 days ago, well below the 72-day median for Analog IC Design roles.
Analog IC Design · Analog Design
|
Open roles in category
315
|
Median days since first seen
72 d
|
Category median salary (all employers)
$143k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (315 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 315 |
| Open roles in the wider Analog & Mixed-Signal family | 5 | 1560 · 118 employers |
| Median days since first seen | 33 d | 72 d (+39 d vs this employer) |
| Median salary (USD postings) | n/a | $143k |
Skills observed across this category: CMOS, Cadence, Transistor-level, Analog IC, PVT Simulation
Who's hiring in this category
- Texas Instruments · 40 open roles · median 72 d
- Analog Devices · 30 open roles · median 39 d
- Renesas Electronics · 24 open roles · median 46 d
- Micron Technology · 22 open roles · median 106 d
- NXP Semiconductors · 17 open roles · median 60 d
- Skyworks · 15 open roles · median 37 d
How we counted: 315 open Analog IC Design (Analog Design) roles from 55 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Analog & Mixed-Signal family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.