Ambient Compute System Architecture and Power Engineer
$148,300 - $222,500 USD yearly
Originally posted 20 July 2026 by the employer.
Focus on performance optimization, data-path analysis, and power modeling across Qualcomm's Low-Power AI (LPAI) subsystems.
About the role
This role is part of Qualcomm's Low-Power AI (LPAI) Systems group and focuses on performance optimization, data-path and power analysis, and architecture of embedded AI subsystems, with an emphasis on XR and ambient use cases. You will analyze power-performance trade-offs across DSP/AI subsystems and enable hardware and software optimizations for on-device AI.
What you'll do
- Analyze and optimize performance and power of LPAI subsystems (DSP, eNPU, memory) with a focus on XR and always-on AI workloads. - Support system integration, benchmarking, and commercialization of LPAI solutions across Mobile, XR, Compute, and IoT platforms. - Perform detailed data-path and memory-access analysis across cache, SRAM, and DDR to identify bottlenecks impacting performance efficiency. - Drive ambient system workload partitioning, software optimizations, clock/BW voting, and data reuse strategies. - Execute lab-based power measurements and correlate silicon data with modeling. - Document performance and power analysis, competitive analysis findings, and architectural recommendations.
What you'll need
- Bachelor's degree in Engineering, Information Systems, Computer Science, or related field with 4+ years of Systems Engineering experience (or Master's with 3+ years, or PhD with 2+ years). - Experience with embedded processor architectures such as DSPs and NPUs, including understanding of processor power behavior. - Experience working with embedded platforms, RTOS, and performance/power profiling tools. - Programming skills in Python for analysis, modeling, and automation. - Understanding of memory systems, data movement, bandwidth analysis, and cache memory strategies. - Background in power modeling, power analysis, system-level power optimization, and power measurement tools. - Knowledge of fixed-point implementation and algorithm optimization techniques.
Nice to have
- Experience with Qualcomm DSP and LPAI architectures, SDKs, or internal power tools. - Background in audio or always-on AI use cases. - Exposure to ML inference workloads and their power-performance characteristics.
Skills: LPAI subsystem, performance and power optimization, workload partitioning, power modeling, embedded processor architectures
This role has been open 91 days — well above the 81-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
470
|
Median days open
81 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (470 roles · 66 employers) |
|---|---|---|
| Open roles in this specialty | 73 | 470 |
| Open roles in the wider Digital Design & Verification family | 392 | 3224 · 116 employers |
| Median days open | 89 d | 81 d (+8 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: LPAI subsystem, performance and power optimization, workload partitioning, power modeling, embedded processor architectures
Who's hiring in this category
- Qualcomm (this employer) · 73 open roles · median 90 d
- NVIDIA · 56 open roles · median 71 d
- Apple · 36 open roles · median 14 d
- AMD · 34 open roles · median 62 d
- Arm Holdings · 27 open roles · median 117 d
- Micron Technology · 22 open roles · median 109 d
How we counted: 470 open SoC/Chip Architecture (SOC Architecture) roles from 66 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.