AI Silicon, Physical Design Engineer
Originally posted October 1, 2026 by the employer.
About the role
You will be responsible for the back-end realization of a novel computing platform, taking complex digital logic from RTL to GDSII.
What you'll do
- Lead the physical implementation of complex, high-performance blocks and top-level SoC integration, including floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and physical verification.
- Drive Power, Performance, and Area (PPA) targets while working closely with architects to influence micro-architecture for routability and timing closure.
- Own the final sign-off process, including Static Timing Analysis (STA), IR drop analysis (static and dynamic), Electromigration (EM), and Physical Verification (DRC/LVS/ERC).
- Contribute to the development and automation of the physical design flow, covering synthesis, formal verification (LEC), and parasitic extraction.
- Work at the interface of digital and analog design to facilitate the integration of custom analog mixed-signal blocks into the digital fabric.
- Evaluate potential partners offering AI tools to improve chip design efficiency.
What you'll need
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of industry experience in digital physical design, with a track record of successful tapeouts on modern process nodes.
- Expertise in Static Timing Analysis (STA) and timing closure for high-frequency, complex designs.
- Understanding of physical design challenges in advanced nodes, including multi-patterning, finFET effects, and low-voltage operation.
- Proficiency in power integrity analysis and noise coupling mitigation.
- Mastery of standard EDA tool suites (Synopsys Fusion Compiler/IC Compiler II or Cadence Innovus) and scripting in Tcl, Python, or Perl.
Nice to have
- Experience with physical design for Machine Learning accelerators or large-scale systolic arrays.
- Experience with top-level integration of large, custom analog macros and complex power-sequencing requirements.
- Hands-on experience with multi-voltage domains, UPF/CPF flows, and advanced power-gating techniques.
- Familiarity with AI tools for chip design.
Skills: physical design, STA, RTL to GDSII, Innovus, timing closure
More semiconductor jobs: Physical design jobs
First seen in our index 0 days ago, well below the 62-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
753
|
Median days since first seen
62 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Unconventional AI | All employers we track in this specialty (753 roles · 90 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 753 |
| Open roles in the wider Physical Implementation family | 2 | 1700 · 123 employers |
| Median days since first seen | 0 d | 62 d (+62 d vs this employer) |
| Median salary (USD postings) | n/a | $187k |
Skills observed across this category: physical design, STA, RTL to GDSII, Innovus, timing closure
Who's hiring in this category
- Qualcomm · 119 open roles · median 66 d
- AMD · 66 open roles · median 45 d
- Broadcom · 53 open roles · median 24 d
- NVIDIA · 46 open roles · median 85 d
- Synopsys · 44 open roles · median 43 d
- Apple · 32 open roles · median 8 d
How we counted: 753 open Physical Design (Physical Design) roles from 90 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Physical Implementation family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.