AI Silicon, Junior Digital Design Engineer
Originally posted April 3, 2026 by the employer. Relisted by the employer on November 14, 2026.
About the role
As an SOC Design Engineer, you will be a foundational member of a small, multi-disciplinary R&D team responsible for prototyping, driving invention, and validating the core digital components of the computing platform.
What you'll do
- Contribute to micro-architecture definition and integration of digital blocks, including CPU, interfaces, memory subsystems, and third-party IP into the main SoC fabric.
- Write clean, synthesizable, and high-performance Verilog/SystemVerilog code for SoC blocks and digital interfaces to meet power, performance, and area (PPA) targets.
- Implement advanced techniques for low-power design, including clock gating and power domains.
- Perform initial synthesis, formal verification (LEC), block-level timing constraint creation, and resolve RTL linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks.
- Participate in block-level verification plans, help develop verification environments, and triage simulation failures.
- Support created technical interfaces and assist in the hand-off between internal design and physical implementation teams.
What you'll need
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- 4+ years of industry experience in digital ASIC/SoC design.
- Expertise in Verilog RTL coding and digital design fundamentals.
- Familiarity with standard EDA tools for simulation, assertions, synthesis, linting, and clock domain crossing (CDC) analysis.
- Understanding of the full ASIC design flow, from specification to tape-out.
Nice to have
- Experience with design constraints or architectures related to Machine Learning/Neural Network accelerators.
- Experience with UVM (Universal Verification Methodology) environments for basic debugging.
- Knowledge of formal verification techniques.
- Exposure to post-silicon bring-up and lab debugging using logic analyzers or oscilloscopes.
- Experience with modern design methods, including generative AI code development platforms.
- Experience integrating large analog mixed-signal blocks into larger subsystems.
More semiconductor jobs: RTL design jobs · Mountain View jobs
First seen in our index 110 days ago, well above the 66-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1070
|
Median days since first seen
66 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Unconventional AI | All employers we track in this specialty (1070 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1070 |
| Open roles in the wider Digital Design & Verification family | 7 | 3639 · 123 employers |
| Median days since first seen | 110 d | 66 d (−44 d vs this employer) |
| Median salary (USD postings) | n/a | $187k |
Who's hiring in this category
- Qualcomm · 147 open roles · median 75 d
- AMD · 92 open roles · median 58 d
- Synopsys · 86 open roles · median 53 d
- NVIDIA · 48 open roles · median 70 d
- NXP Semiconductors · 43 open roles · median 108 d
- Analog Devices · 36 open roles · median 63 d
How we counted: 1070 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.