Originally posted 23 September 2026 by the employer.
About the role
This role involves leading AI/ML initiatives for Design-for-Test (DFT) and Design-for-Debug (DFD) workflows, focusing on improving productivity, quality, scalability, and predictability. The Project Lead will define and drive a portfolio of AI-enabled capabilities within a centralized ASIC design organization.
What you'll do
- Lead the strategy, roadmap, and execution of AI/ML and agentic AI initiatives for DFT and DFD design, methodology, verification, and debug workflows.
- Integrate AI agents and services with DFX design flows, EDA tools, repositories, specifications, regression systems, and engineering data sources.
- Develop AI-enabled expert systems, predictive models, and intelligent automation for DFT challenges across IP, subsystem, and SoC design environments.
- Architect agentic workflows combining large language models, domain knowledge, retrieval, tools, automation, and human-in-the-loop controls.
- Drive scalable DFT implementation and verification automation using Python, Perl, Tcl, and shell scripting within ASIC design environments.
- Coordinate cross-functional project plans, dependencies, risks, milestones, and technical decisions, communicating progress to stakeholders.
What you'll need
- Extensive experience in DFT and/or DFD architecture, design, implementation, verification, or methodology for high-performance SoCs and IP.
- Demonstrated technical leadership of complex, cross-team engineering initiatives from definition through production adoption.
- Hands-on experience developing and deploying AI/ML applications in production or enterprise engineering environments.
- Familiarity with agentic AI systems design, including tool use, multi-agent/subagent systems, Model Context Protocol (MCP), workflow orchestration, Retrieval-Augmented Generation (RAG), structured outputs, evaluation, and human oversight.
- Strong Python development skills and experience with relevant AI/ML frameworks and libraries (e.g., scikit-learn, PyTorch, TensorFlow).
- Experience with software engineering and deployment practices such as source control, code review, automated testing, CI/CD, APIs, containers, and observability.
- Knowledge of MLOps and data lifecycle practices, including data quality, model evaluation, versioning, monitoring, and reproducibility.
- Proficiency with one or more ASIC/EDA automation languages, including Perl, Tcl, and shell scripting.
- Strong foundation in digital logic, VLSI design, and interactions among test, power, timing, area, physical design, and verification constraints.
- Proven ability to influence technical direction across organizational boundaries and convert ambiguous problems into executable project plans.
Nice to have
- Experience integrating AI capabilities with EDA tools, semiconductor design flows, or large-scale engineering automation environments.
- Experience with knowledge representation, engineering specifications, graph-based data, vector search, or domain-specific retrieval systems.
- Familiarity with secure AI deployment, responsible AI practices, access controls, intellectual-property protection, and auditability.
- Python development skills and hands-on development experience with relevant AI/ML frameworks and libraries such as Claude SDK / OpenAI SDK.
- BSEE, MSEE, Computer Engineering, Computer Science, or an equivalent technical degree.
This role has been open 17 days — well below the 54-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
247
|
Median days open
54 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (247 roles · 52 employers) |
|---|---|---|
| Open roles in this specialty | 39 | 247 |
| Open roles in the wider Digital Design & Verification family | 265 | 3166 · 114 employers |
| Median days open | 36 d | 54 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Who's hiring in this category
- AMD (this employer) · 39 open roles · median 37 d
- Qualcomm · 29 open roles · median 94 d
- NVIDIA · 21 open roles · median 53 d
- NXP Semiconductors · 18 open roles · median 93 d
- Synopsys · 12 open roles · median 25 d
- Micron Technology · 11 open roles · median 65 d
How we counted: 247 open DFT Engineering (DFT Test) roles from 52 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.