AI/ML Camera Lead Engineer
$179,000 - $268,400 USD yearly
Originally posted 21 May 2026 by the employer.
About the role
Qualcomm is hiring an AI/ML Camera Lead Engineer within the Camera Engineering group to own ASIC IP blocks and lead GenAI-assisted hardware design workflows. The scope spans camera and ISP micro-architecture, RTL delivery, and deploying agentic AI solutions across digital design and verification pipelines.
What you'll do
- Define and implement micro-architectures for image and video processing pipelines in collaboration with system and camera architects. - Design, implement, and own ASIC IP blocks from architecture through RTL delivery using Verilog/SystemVerilog or VHDL. - Run synthesis, review performance, power, and area (PPA) results, and perform CDC, low-power, timing, and design rule checks. - Work closely with design verification and physical design teams to support test planning, debug, and design closure. - Oversee the design and delivery of an internal benchmark suite for LLMs and agentic AI solutions for hardware design workflows. - Prototype and drive GenAI research directions for chip design, guiding concepts from R&D into internal deployment.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 6+ years of relevant experience (or Master's with 5+ years, or PhD with 4+ years). - Hands-on experience with ASIC RTL design using Verilog/SystemVerilog or VHDL. - Understanding of ASIC design flows including synthesis, timing, CDC, and low-power analysis. - Domain experience with camera/ISP, image processing, video, multimedia, computer vision, or DSP hardware. - Proficiency in Python (and/or C/Java) for tooling, automation, and GenAI evaluation workflows. - Practical experience with LLMs, embedding models, or agentic AI systems applied to engineering workflows.
Nice to have
- Experience with SystemC or hardware modeling. - Prior ASIC implementation of camera or image processing IP. - Experience defining or maintaining benchmarking and evaluation frameworks for ML/LLM systems. - Familiarity with agentic AI frameworks or tools used for code generation, review, or analysis. - Scripting experience in Python, TCL, Perl, or shell supporting RTL or GenAI flows.
Skills: ASIC IP blocks, RTL, Verilog/SystemVerilog, synthesis, GenAI for Hardware Design
This role has been open 154 days — well above the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1084
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1084 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 160 | 1084 |
| Open roles in the wider Digital Design & Verification family | 424 | 3328 · 115 employers |
| Median days open | 60 d | 63 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC IP blocks, RTL, Verilog/SystemVerilog, synthesis, GenAI for Hardware Design
Who's hiring in this category
- Qualcomm (this employer) · 160 open roles · median 60 d
- Synopsys · 87 open roles · median 36 d
- AMD · 77 open roles · median 42 d
- Analog Devices · 49 open roles · median 53 d
- NXP Semiconductors · 42 open roles · median 92 d
- NVIDIA · 39 open roles · median 64 d
How we counted: 1084 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.