AI Lead Architect - Silicon Design Execution - San Jose, California, United States
$206,400 - $303,250 USD yearly
Originally posted 20 September 2026 by the employer — open 0 days.
About the role
This individual contributor role focuses on defining and driving Altera's AI strategy for chip design, leading its deployment into design, verification, and implementation workflows.
What you'll do
- Develop and own the AI/ML strategy for hardware design, verification, and implementation.
- Lead the deployment of AI-driven tools and methods into production design, verification, and implementation flows.
- Build and own the AI tooling stack, including retrieval over design collateral, agentic assistants, and predictive models.
- Establish evaluation, versioning, monitoring, and retirement processes for AI tools.
- Partner with CAD and IT to build the data foundation for ML, ensuring access, provenance, quality, and IP protection.
- Engage with design, verification, DFT, implementation, and EDA tooling teams to co-develop AI-based solutions.
What you'll need
- 12+ years of hands-on experience in semiconductor/hardware design, verification, or implementation, with deep familiarity with EDA tools and flows.
- Demonstrated experience applying AI/ML techniques to engineering workflows, specifically within chip design, verification, or physical implementation.
- Working proficiency in Python and modern ML/LLM tooling, with hands-on experience in LLM fine-tuning, post-training, retrieval-augmented generation over technical corpora, agentic frameworks, or classical ML applied to EDA data (ML-guided placement/routing, predictive timing/power, verification coverage optimization).
- Track record of leading technical initiatives and driving adoption of new methodologies across engineering teams without direct management authority.
- Demonstrated ability to engage senior customers, build rapport, and navigate challenging technical conversations with credibility, diplomacy, and influence.
- Strong written and verbal communication skills, including presenting strategy and progress to senior leadership.
- BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Nice to have
- Prior experience in an EDA company, semiconductor company, or FPGA/ASIC design environment.
- Familiarity with machine learning frameworks and their application to EDA problems (e.g., ML-guided placement/routing, predictive timing/power analysis, verification coverage optimization).
- Experience operating at a senior individual-contributor level (Principal/Distinguished Engineer or equivalent), influencing strategy and roadmap decisions.
- Experience engaging directly with customers or external partners on technical strategy.
Skills: AI/ML, hardware design, EDA tools, design verification, LLM fine-tuning, Python
This role has been open 0 days — well below the 55-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · AI EDA Design
|
Open roles in category
49
|
Median days open
55 d
|
Median salary
$209k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Altera | All employers we track in this specialty (49 roles · 21 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 49 |
| Open roles in the wider Physical Implementation family | 25 | 1382 · 107 employers |
| Median days open | 0 d | 55 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $209k |
Skills observed across this category: AI/ML, hardware design, EDA tools, design verification, LLM fine-tuning, Python
Who's hiring in this category
- NXP Semiconductors · 10 open roles · median 49 d
- Cadence Design Systems · 6 open roles · median 28 d
- NVIDIA · 5 open roles · median 60 d
- Qualcomm · 4 open roles · median 48 d
- Micron Technology · 3 open roles · median 136 d
- Synopsys · 3 open roles · median 33 d
How we counted: 49 open EDA/CAD Engineering (AI EDA Design) roles from 21 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.