AI Design Automation Engineer - CA, San Jose, United States
Originally posted 10 September 2026 by the employer.
Build AI-powered engineering platforms that enable chip design teams to interact with complex semiconductor design data.
About the role
As an AMD-AECG Design Automation Engineer, you will help build AI-powered engineering platforms that enable AMD's chip design teams to find, understand, and interact with complex semiconductor design data. You will develop scalable software systems, data pipelines, knowledge graphs, and AI/LLM-driven capabilities.
What you'll do
- Design, build, and maintain backend data pipelines that turn engineering data sources into structured, queryable representations.
- Design and evolve data schemas and queries to support new engineering data types and use cases at production scale.
- Build and extend AI/LLM-based components that let engineers query and interact with engineering data using natural language.
- Diagnose and fix reliability and performance issues in distributed batch-processing pipelines handling large volumes of data.
- Design and implement new data pipelines to bring additional engineering data domains onto the platform.
- Tune LLM-based components for accuracy, cost, and latency.
- Own a TDD-driven development workflow using the team's version control and code review practices.
- Collaborate with architecture, verification, and design teams to translate their data and workflow needs into platform capabilities.
What you'll need
- Strong software engineer with experience building production-quality backend systems.
- Comfortable designing data models and building large-scale data pipelines.
- Experience developing AI/LLM-based solutions such as retrieval systems, knowledge graphs, and agentic workflows.
- Bachelors/Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
Nice to have
- Strong Python engineering background, with rigorous testing discipline (unit/integration/end-to-end) in a large, shared codebase.
- Experience with graph databases and/or vector search systems, including schema design and query performance for retrieval workloads.
- Experience with LLM-based/agentic systems: retrieval-augmented generation, agent orchestration frameworks, tool-use/function-calling, and awareness of LLM cost/latency/token tradeoffs.
- Familiarity with RTL/HDL/Physical Design semantics (SystemVerilog/Verilog/SW/HW modeling, module hierarchy, instantiation, parameters) and toolchains for parsing/elaborating hardware design source.
- Experience with time-series/relational data stores and reasoning about consistency across multiple database backends.
- Strong written and verbal communication skills.
Skills: AI-powered engineering platforms, data pipelines, knowledge graphs, LLM-driven capabilities, semiconductor design data
This role has been open 34 days — below the 35-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · AI EDA Design
|
Open roles in category
64
|
Median days open
35 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (64 roles · 23 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 64 |
| Open roles in the wider Physical Implementation family | 85 | 1469 · 108 employers |
| Median days open | 50 d | 35 d (+15 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: AI-powered engineering platforms, data pipelines, knowledge graphs, LLM-driven capabilities, semiconductor design data
Who's hiring in this category
- NXP Semiconductors · 13 open roles · median 56 d
- NVIDIA · 8 open roles · median 28 d
- Keysight Technologies · 7 open roles · median 15 d
- Cadence Design Systems · 6 open roles · median 52 d
- Skyworks · 3 open roles · median 0 d
- Synopsys · 3 open roles · median 40 d
How we counted: 64 open EDA/CAD Engineering (AI EDA Design) roles from 23 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.