AI Core DV Engineer - Mountain View, CA, United States
$180,000 - $275,000 USD yearly
Originally posted 2 June 2026 by the employer.
Own verification of our AI compute core.
About the role
This role involves owning the verification of DensityAI's AI compute core, including tensor pipelines, MAC arrays, accumulator logic, and the compute ↔ memory interconnect. This work is critical to driving DensityAI's AI accelerator program.
What you'll do
- Own verification of our AI compute core - tensor pipelines, MAC arrays, accumulator logic, and the compute ↔ memory interconnect
What you'll need
- 5+ years of experience verifying compute-heavy blocks (CPU (floating point), GPU, NPU, DSP, or AI accelerator)
- Abilities in arithmetic and datapath verification (tensor pipelines, MAC arrays, FP / INT accumulators)
- Proficient in C++, SystemVerilog, UVM, and Python
- Hands-on with verification methodology - constrained-random verification, coverage-driven closure, and debug across long pipelines
Nice to have
- Strong understanding of numerical correctness (FP rounding, denormals, saturation) and golden-model comparison
- Familiarity with formal methods (FPV, DPV), writing custom golden models in C++ or Python
- Familiarity with a commercial formal tool like JasperGold or VC_Formal
Skills: AI compute core, tensor pipelines, MAC arrays, SystemVerilog, UVM, datapath verification
This role has been open 34 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | DensityAI | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1192 |
| Open roles in the wider Digital Design & Verification family | 5 | 3189 · 115 employers |
| Median days open | 34 d | 65 d (−31 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: AI compute core, tensor pipelines, MAC arrays, SystemVerilog, UVM, datapath verification
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.