Originally posted 29 September 2026 by the employer.
About the role
This intern role focuses on exploring AI-assisted and self-adaptive memory design techniques that optimize memory operation for improved performance, power efficiency, and yield.
What you'll do
- Analyze conventional memory assist techniques and explore how AI/ML-driven learning and optimization can enhance control logic, supply modulation, boosted/negative voltages, and replica/tracking schemes.
- Investigate AI/ML-based techniques to analyze memory operating conditions, identify failure signatures, and predict robustness across voltage, temperature, process variation, timing, and parasitic effects.
- Explore self-timed, self-adaptive, and intelligent memory techniques that learn from operating conditions and dynamically optimize assist decisions for improved robustness, power, performance, and yield.
- Develop AI/ML-assisted monitoring, prediction, and adaptive control techniques for dynamically optimizing memory assist, voltage, timing, and read/write operations.
- Document, benchmark, and present proposed self-adaptive memory architecture and key design insights.
What you'll need
- Pursuing a BS in EE, CE, Microelectronics, or related field (rising Junior/Senior).
- Coursework in Digital Integrated Circuits, Analog Circuit Design, VLSI Design, or Semiconductor Devices.
- Coursework in Machine Learning, Optimization, Data Analytics, Computational Methods or related courses.
- Basic understanding of CMOS circuit design and IC layout (DRC/LVS) concepts.
- Working knowledge of Python and basic ML concepts (regression, clustering).
- Comfort working with large datasets.
- Strong analytical and problem-solving ability.
Nice to have
- Exposure to layout/schematic tools (Virtuoso, Calibre) or characterization tools (SiliconSmart, PrimeTime, Liberate).
- Interest in low-power IP for edge AI/IoT.
- Strong passion, eagerness, and curiosity to learn and explore transistor-level circuit design.
Skills: memory design, AI/ML-driven learning, control logic, CMOS circuit design, power efficiency
More semiconductor jobs: Singapore jobs
This role has been open 37 days — well below the 72-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
302
|
Median days open
72 d
|
Category median salary (all employers)
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ambiq Micro | All employers we track in this specialty (302 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 302 |
| Median days open | 71 d | 72 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: memory design, AI/ML-driven learning, control logic, CMOS circuit design, power efficiency
Who's hiring in this category
- Micron Technology · 154 open roles · median 82 d
- Synopsys · 30 open roles · median 77 d
- Qualcomm · 18 open roles · median 106 d
- Broadcom · 16 open roles · median 78 d
- SanDisk · 15 open roles · median 7 d
- NVIDIA · 8 open roles · median 59 d
How we counted: 302 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.