AI Architect, Agentic AI for Chip Design & EDA - San Jose, California, United States
$209,500 - $295,000 USD yearly
Originally posted 7 October 2026 by the employer.
About the role
This role leads the development of Agentic AI, Generative AI, and machine learning technologies to transform the end-to-end silicon development lifecycle. The position focuses on AI-powered semiconductor design solutions, from architecture and RTL development through physical design, manufacturing, and yield optimization.
What you'll do
- Lead the strategy, architecture, and development of AI-driven solutions for semiconductor design and optimization.
- Develop and deploy Agentic AI systems to automate complex engineering workflows across RTL, synthesis, physical design, signoff, DRC, power planning, validation, and 3D-IC design.
- Advance domain-specific Large Language Models (LLMs) and foundation models tailored for semiconductor workflows.
- Lead AI initiatives that improve chip Power, Performance, Area (PPA), manufacturability, reliability, and silicon yield.
- Architect enterprise-scale AI and analytics platforms supporting EDA workloads and semiconductor design data.
- Drive Design Technology Co-Optimization (DTCO) initiatives linking design, process development, manufacturing, and yield learning.
What you'll need
- Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a related technical field.
- 12+ years of semiconductor industry experience with expertise spanning multiple phases of the silicon lifecycle.
- Deep understanding of digital IC design, RTL development, synthesis, physical implementation, timing closure, verification, and signoff methodologies.
- Strong expertise in AI/ML technologies, including Generative AI, LLMs, reinforcement learning, graph neural networks, and predictive modeling.
- Advanced programming skills in Python and one or more of C/C++, Java, or similar languages.
- Experience building enterprise software, AI platforms, analytics applications, or automation systems.
- Proven technical leadership experience leading large-scale engineering initiatives.
- Strong understanding of semiconductor manufacturing, yield analysis, DTCO, or design enablement.
Nice to have
- Experience developing Agentic AI systems for engineering or semiconductor applications.
- Hands-on expertise with leading EDA tools and workflows from Cadence, Synopsys, Siemens EDA, or equivalent platforms.
- Experience developing domain-specific LLMs, RAG architectures, AI copilots, or autonomous workflow solutions.
- Expertise with cloud computing, distributed systems, Spark, data engineering, and large-scale AI infrastructure.
- Knowledge of 3D-IC, advanced packaging, silicon photonics, advanced process technologies, or foundry operations.
- Track record of patents, publications, conference presentations, or industry-recognized technical contributions.
- Experience leading global, multidisciplinary engineering teams.
Skills: AI Architect, Agentic AI for Chip Design & EDA, AI-powered semiconductor design solutions, autonomous chip design, AI-driven design solutions
This role has been open 1 day — well below the 34-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · AI EDA Design
|
Open roles in category
61
|
Median days open
34 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Altera | All employers we track in this specialty (61 roles · 23 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 61 |
| Open roles in the wider Physical Implementation family | 30 | 1488 · 107 employers |
| Median days open | 1 d | 34 d (−33 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: AI Architect, Agentic AI for Chip Design & EDA, AI-powered semiconductor design solutions, autonomous chip design, AI-driven design solutions
Who's hiring in this category
- NXP Semiconductors · 12 open roles · median 57 d
- Cadence Design Systems · 7 open roles · median 30 d
- Keysight Technologies · 7 open roles · median 9 d
- NVIDIA · 7 open roles · median 29 d
- Qualcomm · 3 open roles · median 46 d
- Altera (this employer) · 2 open roles · median 10 d
How we counted: 61 open EDA/CAD Engineering (AI EDA Design) roles from 23 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.