Advanced Package Technology, Principal Engineer - Hsinchu City, Taiwan
Originally posted 2 September 2026 by the employer.
About the role
This role involves developing advanced packaging technology to meet electrical, mechanical, thermal, and system requirements for high performance computing (HPC), Artificial Intelligence (AI), and networking solutions. This includes developing technology roadmaps for AI XPU, XPU-attach, and Switch, with a focus on 2.5D and 3D packages, Co-packaged optics, and advanced substrates.
What you'll do
- Develop packaging technology roadmaps for AI XPU, XPU-attach, and Switch.
- Define package architecture including chiplet topology, interposer/substrate scaling, and power delivery network strategy.
- Lead co-design efforts across silicon design, floorplanning, power delivery network (PDN) modeling, and mechanical/thermal reliability.
- Partner with silicon design teams to co-optimize die floorplan, bump map, TSV, and RDL requirements.
- Work with OSATs / Foundry partners to evaluate process capability, manufacturability, yield, and cost.
- Drive package qualification and reliability validation to volume readiness.
What you'll need
- Experience in advanced package and substrate technologies with deep understanding of process and materials.
- Knowledge of component and board level reliability, warpage, and thermal management.
- Deep knowledge of Electrical Engineering concepts, circuit extractions, and simulation.
- Experience in signal integrity and power integrity simulations, analysis, and optimization for 2.5D and 3D packages.
- Understanding of signal integrity, power integrity, transmission line, and electromigration concepts for 2.5D/3D package technology including CoWoS-S/R/L, EMIB-T, Co-packaged optics (CPO), and chip-package co-design (CPC).
- Proficiency with Cadence Sigrity PowerSI, Ansys SIwave, Ansys HFSS, and Cadence Clarity for signal and power integrity analyses.
- Bachelor’s or Master’s degree in Mechanical Engineering, Material Science, or related fields with 8-10 years of experience, or PhD with 5+ years of experience.
Nice to have
- Experience in data center AI accelerators, networking silicon, or custom HPC silicon.
- Experience with silicon disaggregation and reaggregation and memory integration.
- Experience with VNA and TDR measurements for package and PCB characterization.
Skills: 2.5D and 3D packages, Co-packaged optics, chiplet topology, signal integrity, power integrity
This role has been open 27 days — well below the 84-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
39
|
Median days open
84 d
|
Median salary
$217k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (39 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 39 |
| Median days open | 27 d | 84 d (−57 d vs this employer) |
| Median salary (USD postings) | — | $217k |
Skills observed across this category: 2.5D and 3D packages, Co-packaged optics, chiplet topology, signal integrity, power integrity
Who's hiring in this category
- Marvell Technology (this employer) · 5 open roles · median 27 d
- Qualcomm · 5 open roles · median 91 d
- Micron Technology · 4 open roles · median 138 d
- NVIDIA · 4 open roles · median 50 d
- Intel Corporation · 3 open roles · median 25 d
- AMD · 2 open roles · median 53 d
How we counted: 39 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 18 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.