Accelerator Compiler and Tool Chain Lead - Santa Clara, CA, United States

Originally posted 16 July 2026 by the employer.

Lead the path from customer AI models to optimized executable artifacts for Velaura’s AI accelerator.

About the role

This role will own the compiler and model-lowering stack for Velaura’s AI accelerator, leading the path from customer AI models to optimized executable artifacts for our NPU.

What you'll do

• Lead architecture and development of the AI accelerator compiler stack.
• Own model ingestion and graph lowering from frameworks and exchange formats such as PyTorch export flows, ONNX, TensorFlow Lite, or similar.
• Define operator coverage strategy, lowering rules, graph transformations, fusion, partitioning, and fallback behavior.
• Develop compiler optimization passes for tensor layout, tiling, memory movement, mixed precision, operator fusion, and hardware-specific scheduling.
• Partner with hardware architecture and NPU firmware teams on ISA, command streams, tensor layouts, data movement, hardware constraints, and compiler-visible performance features.
• Own quantization compiler integration, including calibration metadata, precision selection, scale handling, layout constraints, and accuracy/performance tradeoffs.

What you'll need

• Deep experience with compiler development, ML graph compilers, or code generation for accelerators, GPUs, DSPs, or heterogeneous compute systems.
• Strong understanding of ML model formats, graph IRs, operator lowering, tensor layouts, quantization, and runtime/compiler interfaces.
• Strong C++ and Python programming skills and experience building production-quality compiler or systems software.
• Experience with compiler frameworks or technologies such as MLIR, LLVM, TVM, XLA, IREE, Glow, TensorRT-like systems, OpenVINO-like systems, or equivalent.
• Strong understanding of correctness risks in compiler optimizations, graph rewrites, mixed precision, operator fusion, and hardware-specific lowering.
• Experience leading technical teams or major architecture areas.

Nice to have

• Experience with NPU, GPU, DSP, or AI accelerator compiler stacks.
• Experience with quantization-aware compilation, mixed precision, sparsity, pruning, graph partitioning, or hardware-specific scheduling.
• Experience supporting ONNX, PyTorch export, TensorFlow Lite, JAX/XLA, TorchDynamo/TorchInductor, or other model import flows.
• Familiarity with robotics, computer vision, CNNs, transformers, detection, segmentation, depth, SLAM-adjacent perception, or edge AI workloads.
• Experience building customer-facing compiler diagnostics and model-porting tools.
• Experience with model-zoo release processes, accuracy validation, and reproducible benchmark artifacts.
• Open-source compiler contributions or experience working with external framework communities.

Skills: AI accelerator compiler stack, model ingestion, operator coverage, compiler optimization passes, hardware constraints