3DIC Platform Wet and Plating Development Manager - Oregon, Hillsboro, United States
$180,770 - $255,200 USD yearly
Originally posted 9 October 2026 by the employer.
Drive the development and implementation of Wet Clean/Plating processes critical to Intel's Foveros Direct, Foveros, and EMIB technologies.
About the role
As the 3DIC Platform Wet and Plating Development Manager, you will lead the Wet Etch/Clean and Plating technology development for 3DIC platforms. This role drives the development and implementation of Wet Clean/Plating processes critical to Intel's advanced packaging portfolio, including Foveros Direct, Foveros, and EMIB technologies.
What you'll do
- Lead and manage a team of engineers, providing goal setting, performance management, and coaching.
- Formulate long-term strategies for process roadmap to meet future requirements in advanced packaging.
- Oversee development of production-worthy wet etch/plating processes for high-volume manufacturing.
- Drive talent development for technical roles and foster technical excellence and innovation within the wet etch(clean)/plating team.
- Develop and execute project schedules, track milestones, and ensure timely feedback between cross-functional teams.
- Drive Wet Etch(clean) and Plating module and segment related yield improvement initiatives and defect reduction programs.
What you'll need
- Master or PhD degree in Chemistry, Materials Science, Physics, Electrical Engineering, Mechanical Engineering, or a related field.
- 8+ years of relevant experience with a Master's degree, or 6+ years with a PhD degree.
- Experience with Wet Etch/Clean or Plating, including hands-on experience with various wet etch and/or plating platforms.
- Project management experience, including developing schedules, tracking deliverables, and managing cross-functional collaborations.
Nice to have
- Experience building and leading effective teams, fostering an inclusive, productive, and innovative team culture.
- Experience with vendor relations, including material quality assessments and performance management.
- Strong knowledge of Design of Experiments (DOE) principles, problem-solving methodologies, and package interconnect technologies.
Skills: 3DIC platform, wet etch, plating, Foveros, EMIB
This role has been open 2 days — well below the 60-day median for Packaging Engineering roles.
Packaging Engineering · Advanced Packaging
|
Open roles in category
311
|
Median days open
60 d
|
Median salary
$167k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (311 roles · 60 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 311 |
| Open roles in the wider Process, Fab & Equipment family | 174 | 9738 · 108 employers |
| Median days open | 54 d | 60 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $167k |
Skills observed across this category: 3DIC platform, wet etch, plating, Foveros, EMIB
Who's hiring in this category
- KLA Corporation · 48 open roles · median 122 d
- Micron Technology · 36 open roles · median 35 d
- Renesas Electronics · 23 open roles · median 41 d
- Infineon Technologies · 16 open roles · median 60 d
- Intel Corporation (this employer) · 15 open roles · median 54 d
- GlobalFoundries · 13 open roles · median 60 d
How we counted: 311 open Packaging Engineering (Advanced Packaging) roles from 60 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.