3D Stacked Logic Design Engineer - San Jose, CA, United States
$150,000 - $260,000 USD yearly
Originally posted 16 July 2026 by the employer.
Design digital IP for 3D-stacked DRAM.
About the role
This role involves driving the co-design of 3D-stacked DRAM logic dies and providing digital IP services for 3D-stacked DRAM.
What you'll do
- Strengthen leadership in the DRAM-on-Logic era through advanced digital IP design for 3D-stacked DRAM.
- Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for customers.
- Co-design 3D-stacked DRAM Logic Dies with U.S.-based customers.
- Design high-speed digital IP for 3D-stacked DRAM peripheral circuits and DRAM DFT, covering RTL design to implementation.
- Conduct foundry verification of service-ready IPs and set up infrastructure for the IP business.
- Establish close technical engagement with foundry partners to build digital IP for 3D-stacked DRAM.
What you'll need
- Bachelor’s degree or higher in Electrical Engineering or a related discipline with 5+ years of relevant experience.
- Development of Digital Logic IP/SoC based on Hardware Description Languages (Verilog, VHDL).
- Experience in RTL design and implementation memory PHY, hard macro IP for high-speed circuit, or high-speed digital IP design.
- Experience with memory controllers.
- Experience in memory Built-in Self-Test (BIST), DRAM Design for Test (DFT) / Design for Debug (DFD).
- Deep understanding of PPA analysis and optimization, and physical design.
Skills: 3D-Stacked DRAM, Digital Logic IP, RTL design, memory controllers, DRAM DFT
This role has been open 80 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SK Hynix America | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 287 |
| Median days open | 68 d | 69 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: 3D-Stacked DRAM, Digital Logic IP, RTL design, memory controllers, DRAM DFT
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.