3D Stacked DRAM Design Engineer

Focus on 3D-stacked DRAM logic dies and DRAM-on-Logic architecture co-design.

Originally posted 16 July 2026 by the employer.

About the role

This role drives the co-design of 3D-stacked DRAM logic dies and DRAM-on-Logic solutions in collaboration with U.S.-based customers. You will design circuits for 3D-stacked DRAM, define product architectures, and implement DRAM DFT to meet customer specifications.

What you'll do

• Co-design 3D-stacked DRAM logic dies and DRAM-on-Logic solutions with U.S.-based customers.
• Design circuits for 3D-stacked DRAM that meet internal and external specifications, including DRAM DFT implementation.
• Review specifications and define architecture for 3D-stacked DRAM products.
• Improve design quality and yield throughout the 3D-stacked DRAM development phase.
• Enhance performance and ensure stable operation to meet customer requirements during product development.
• Establish technical engagement with U.S.-based customers to address immediate 3D-stacked DRAM design challenges.

What you'll need

• Bachelor’s degree or higher in Electrical Engineering or a related discipline with 4+ years of relevant experience.
• Experience with DRAM development and DRAM circuit design using custom design methodology (Virtuoso or similar tools, SPICE simulator).
• Experience reviewing DRAM specifications and architecture.
• Experience in full custom + digital co-design and PDN analysis.
• Experience in full custom-based logic foundry design.
• Experience evaluating compliance with DRAM specifications through design analysis at wafer level test, package level test, or system level test.
• Expertise in Python and circuit simulators such as HSPICE, PrimeSim, or Spectre.

Skills: 3D-stacked DRAM, DRAM peripheral circuits, DRAM DFT, custom design methodology, circuit design

More semiconductor jobs: San Jose jobs