3D IC and SoC CAD ENGINEER - TX, Austin, United States
Originally posted 30 September 2026 by the employer.
About the role
This role involves implementing and maintaining automated environments for 3D IC stack and advanced packaging design methodologies. The team delivers flows encompassing 3D netlist and physical design, advanced packaging implementation, and 3D analysis across EMIR, PERC/ESD, physical verification, and STA.
What you'll do
- Implement and maintain 3D-IC and advanced packaging design flows from RTL through signoff.
- Lead hands-on debug and automation involving large chip level physical and logical netlists.
- Partner with EDA vendors (Synopsys, Cadence) on 3D-IC feature requirements and enhancement requests.
- Develop and integrate end-to-end AI capabilities into CAD flows, including ML-based optimization, predictive modeling, and LLM-assisted automation.
- Define strategy and key initiatives to ensure flows meet future design requirements and advanced technology nodes.
- Regress methodology, analyze results, and develop capabilities that measurably improve quality of results.
What you'll need
- Strong silicon hardware design background.
- Scripting proficiency.
- Hands-on experience applying machine learning to CAD or EDA workflows.
- Bachelors or Masters degree in computer engineering/Electrical Engineering.
Nice to have
- Strong understanding of industry EDA tools, with emphasis on place-and-route, extraction, and analysis tools (e.g., ICC2, Innovus, Primetime).
- Familiarity with chip- or system-level netlists and ability to debug connectivity across industry-standard formats (DEF/LEF/SPEF/Verilog/UPF/OAS/GDS).
- Exposure with system level design verification processes including LEC, LVS, DRC.
- Comfort navigating large datasets and utilizing automation, distributed and cloud compute environments.
- Demonstrated experience applying AI (ML-based optimization, LLM-assisted automation, agentic frameworks) to CAD, EDA, or hardware design problems.
- Strong scripting skills in Python, TCL, and Perl within a Linux/Unix environment.
- Experience with advanced-node tapeouts across silicon technologies.
- Exposure to Advanced Packaging technologies (2.5D, 3D, 3.5D, including interposers and silicon bridges).
- Exposure to chip-level construction (PDN, bump planning) and analysis.
This role has been open 9 days — well below the 79-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
704
|
Median days open
79 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (704 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 23 | 704 |
| Open roles in the wider Physical Implementation family | 89 | 1485 · 107 employers |
| Median days open | 18 d | 79 d (−61 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Who's hiring in this category
- Cadence Design Systems · 163 open roles · median 162 d
- Synopsys · 59 open roles · median 36 d
- Micron Technology · 44 open roles · median 107 d
- Qualcomm · 42 open roles · median 60 d
- NVIDIA · 41 open roles · median 73 d
- GlobalFoundries · 30 open roles · median 51 d
How we counted: 704 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.