2027 Masters Hardware Design Verification Engineering Intern/Co-op - TX, Austin, United States
Originally posted 20 August 2026 by the employer.
About the role
This role is for a Hardware Design Verification engineering intern/co-op focused on the design, build, and delivery of high-end Machine Intelligence products.
What you'll do
- Collaborate with senior engineers and/or designers to build and complete performance verification test plans, simulation test cases, and models.
- Write scripts related to tracking and managing compute resources using Perl/Python.
- Support debugging, improving test cases/models, and Verilog/SystemVerilog coding.
- Build test platforms and perform system level testing.
- Engage in low level testing of hardware/software features, debugging technical issues, and identifying root causes.
What you'll need
- Currently enrolled in a United States based University in a Master's program majoring in Electrical Engineering, Computer Engineering, or a related field.
- Knowledge/experience with C++, Python, C, Perl, Shell, UVM.
- Knowledge/experience with Verilog and SystemVerilog.
- Understanding of digital systems and computer organization.
- Knowledge/experience with Linux/Unix/Windows environments.
- Fundamentals of logic design (FSM, gates, registers, flops, timing, HDL).
Skills: Verilog, SystemVerilog, UVM, simulation, test plan
This role has been open 55 days — below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1195
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1195 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 97 | 1195 |
| Open roles in the wider Digital Design & Verification family | 255 | 3183 · 115 employers |
| Median days open | 51 d | 64 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: Verilog, SystemVerilog, UVM, simulation, test plan
Who's hiring in this category
- Qualcomm · 109 open roles · median 37 d
- AMD (this employer) · 97 open roles · median 51 d
- NVIDIA · 84 open roles · median 58 d
- Synopsys · 63 open roles · median 31 d
- SiFive · 55 open roles · median 73 d
- Arm Holdings · 49 open roles · median 101 d
How we counted: 1195 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.